The Default Assignment Trick
Complex combinational logic blocks, such as state machine output decoders, often drive dozens of control signals across various conditions. If a hardware designer forgets to assign a value to a signal in every possible branch of an if-else or case statement, synthesis tools will infer an unwanted latch to hold the previous value. The most robust way to prevent latches and reduce code size is to assign a default value to every output at the very top of the always_comb block, allowing subsequent specific conditions to override those defaults.
The solution module is a memory controller command decoder. It evaluates a 3-bit state and a 2-bit opcode to drive four combinational control signals: mem_read, mem_write, addr_update, and ready.
By default, all control signals must be 0. The outputs change from their default values only under the following specific conditions: • During the IDLE state (3'b000) and the HALT state (3'b100), the ready signal is asserted to 1. • During the FETCH state (3'b001), both mem_read and addr_update are asserted to 1. • During the EXECUTE state (3'b010), mem_write is asserted to 1 if the opcode is 2'b10. • During the EXECUTE state (3'b010), mem_read is asserted to 1 if the opcode is 2'b01.
All other unmapped states and opcode combinations must output the default values.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | state | input | 3 | Current state of the controller | | opcode | input | 2 | Instruction opcode | | mem_read | output | 1 | Memory read enable | | mem_write | output | 1 | Memory write enable | | addr_update | output | 1 | Address register update enable | | ready | output | 1 | Controller ready flag |
Constraints
- The design must be purely combinational.
- No latches may be inferred.
- All unmapped states and opcodes must safely default to all zeros.
- Do not use sequential logic (
always @(posedge clk)); usealways_comboralways @(*).
Topics
Solve this problem
Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.