Typedef Enum State Machine

Memory arbiters require clear, unambiguous state definitions to manage access requests safely. Magic numbers for states make RTL unmaintainable and harder to debug in simulation waveforms. SystemVerilog strongly typed enums solve this by mapping meaningful names to state encodings while preventing accidental integer assignments.

The module is a simple memory access FSM that arbitrates between read and write requests. It waits in an idle state. When a read request arrives, it transitions to a read state and grants read access. If no read request exists but a write request is active, it transitions to a write state and grants write access. Read requests have strict priority over write requests. The FSM remains in the active state until its corresponding request is de-asserted, at which point it unconditionally returns to the idle state before serving any new requests.

Positive-edge triggered clock clk and asynchronous active-low reset rst_n govern the module. On reset, the state machine enters the idle state and all grants are de-asserted. Priority is evaluated only when transitioning out of the idle state.

Worked Trace

Cycle 1: rst_n=0 → current_state=0 (IDLE), grant_read=0, grant_write=0 Cycle 2: rst_n=1, req_read=0, req_write=1 → current_state=2 (WRITE), grant_write=1 Cycle 3: req_read=1, req_write=1 → current_state=2 (WRITE) (hold active state) Cycle 4: req_write=0, req_read=0 → current_state=0 (IDLE) (return to idle) Cycle 5: req_read=1, req_write=0 → current_state=1 (READ), grant_read=1 Cycle 6: req_read=1, req_write=1 → current_state=1 (READ) (hold active state)

State Diagram

flowchart LR
    RESET(( )) -->|reset| IDLE
    IDLE((IDLE)) -->|req_read=1| READ
    IDLE -->|req_read=0, req_write=1| WRITE
    IDLE -->|req_read=0, req_write=0| IDLE
    READ(["READ ★"]):::out -->|req_read=0| IDLE
    READ -->|req_read=1| READ
    WRITE(["WRITE ★"]):::out -->|req_write=0| IDLE
    WRITE -->|req_write=1| WRITE
    classDef out fill:#6C5CE7,stroke:#5B4FE8,color:#fff

Timing Diagram

{ "signal": [
  { "name": "clk",           "wave": "p......" },
  { "name": "rst_n",         "wave": "01....." },
  { "name": "req_read",      "wave": "0.1011" },
  { "name": "req_write",     "wave": "011001" },
  {},
  { "name": "current_state", "wave": "======", "data": ["0", "2", "2", "0", "1", "1"] },
  { "name": "grant_read",    "wave": "0...1." },
  { "name": "grant_write",   "wave": "01.0.." }
], "head": { "text": "FSM behavior showing write grant, hold on read request, return to idle, then read grant." } }

Port Table

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; state goes to IDLE when asserted | | req_read | input | 1 | Request for read access | | req_write | input | 1 | Request for write access | | grant_read | output | 1 | Asserted when FSM is in the READ state | | grant_write | output | 1 | Asserted when FSM is in the WRITE state | | current_state| output | 2 | Current state encoding (0=IDLE, 1=READ, 2=WRITE) |

Constraints

• The design must use a strongly typed enum for the state variable.
• The enum definition must be: typedef enum logic [1:0] {IDLE = 2'b00, READ = 2'b01, WRITE = 2'b10} state_t;
• SystemVerilog strictly enforces typed enums. You cannot assign an untyped integer (e.g., 2'b01) directly to a variable of type state_t. You must use the enum labels (e.g., READ).
• Read requests have strict priority over write requests when evaluated from the IDLE state.
• Once in READ or WRITE, the FSM must ignore new requests until the active request drops and the FSM returns to IDLE.
• Outputs grant_read and grant_write are combinational functions of the current state (Moore outputs).

Topics

Related problems

• Serial Adder Mealy MachineMedium
• Three Process Moore FSM TemplateEasy
• Lookahead FSM Sequence DetectorHard
• Traffic Light Controller with TimerMedium
• Arbiter FSM with Fixed PriorityHard
• One Hot Encoding Flip Flop CountMedium
• Safe FSM Default RecoveryMedium
• Glitch Free Gray Code FSMHard