Nonoverlapping Sequence Detector with Abort

Protocol parsers and frame synchronizers rely on sequence detectors to identify start-of-frame markers in serial data streams. When a communication link experiences an error, a higher-level controller will assert an abort signal to immediately halt parsing and wait for a fresh frame.

The seq_detector module monitors a serial input stream seq_in and asserts the detected output for exactly one clock cycle immediately following the successful reception of the sequence 1011. The detection must be strictly non-overlapping; after a successful detection, the FSM resets its search, meaning the sequence 1011011 will only trigger a single detection. If the abort signal is asserted at any time, the FSM immediately abandons its current progress and returns to the initial search state on the next clock edge.

Clock edge: posedge clk Reset type: Asynchronous, active-low rst_n Reset values: FSM returns to IDLE, detected becomes 0 Priority rules: abort has strict priority over seq_in. If abort is 1, the FSM must transition to IDLE regardless of the value of seq_in.

Cycle 1: rst_n=0 → state=IDLE, detected=0 Cycle 2: rst_n=1, abort=0, seq_in=1 → state=S1, detected=0 Cycle 3: abort=0, seq_in=0 → state=S10, detected=0 Cycle 4: abort=0, seq_in=1 → state=S101, detected=0 Cycle 5: abort=0, seq_in=1 → state=DETECT, detected=1 (Sequence 1011 complete) Cycle 6: abort=0, seq_in=1 → state=S1, detected=0 (Non-overlapping: evaluates the new '1' as start of next sequence) Cycle 7: abort=0, seq_in=0 → state=S10, detected=0 Cycle 8: abort=1, seq_in=1 → state=IDLE, detected=0 (abort overrides seq_in)

flowchart LR
    RESET(( )) -->|rst_n=0| IDLE
    IDLE -->|in=1| S1
    IDLE -->|in=0| IDLE
    S1 -->|in=0| S10
    S1 -->|in=1| S1
    S10 -->|in=1| S101
    S10 -->|in=0| IDLE
    S101 -->|in=1| DETECT
    S101 -->|in=0| S10
    DETECT(["DETECT ★"]):::out -->|in=1| S1
    DETECT -->|in=0| IDLE
    classDef out fill:#6C5CE7,stroke:#5B4FE8,color:#fff

*(Note: For diagram clarity, the synchronous abort transitions are omitted, but an asserted abort forces a transition to IDLE from any state).*

{ "signal": [
  { "name": "clk",      "wave": "p......." },
  { "name": "rst_n",    "wave": "01......" },
  { "name": "abort",    "wave": "0......1" },
  { "name": "seq_in",   "wave": "01011101" },
  {},
  { "name": "state",    "wave": "========", "data": ["IDLE", "S1", "S10", "S101", "DETECT", "S1", "S10", "IDLE"] },
  { "name": "detected", "wave": "0...10.." }
], "head": { "text": "Detection of 1011 followed by a new sequence start and an abort." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; FSM goes to IDLE and detected goes to 0 | | seq_in | input | 1 | Serial data input stream | | abort | input | 1 | Synchronous abort; forces FSM to IDLE on the next clock edge | | detected | output | 1 | Asserted high for one cycle immediately after 1011 is fully received |

Constraints

• Clock edge and reset polarity: posedge clk, active-low asynchronous rst_n.
• Output values on reset: detected must be 0.
• Priority: abort has strict priority over seq_in. If abort is 1, the FSM must transition to IDLE regardless of seq_in.
• Non-overlapping: The FSM must reset its search after a successful detection. The bit evaluated during the DETECT state is treated as the first bit of a potential new sequence.
• Output timing: detected must be high for exactly one clock cycle immediately following the successful reception of the final '1' in 1011. A Moore machine where the output is tied to a specific state is required to meet this timing.

Topics

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