Explicit One Hot Encoding

High-speed digital designs often require state machines to operate with minimal combinational logic delay. By explicitly encoding states using a one-hot format, the next-state logic is simplified to fast bitwise operations. This module implements an overlapping sequence detector that identifies the bit pattern 1011 from a serial input stream. To guarantee synthesis tools do not compress the state registers into a dense binary encoding, the FSM explicitly exposes its internal 5-bit one-hot state vector as an output.

The state machine must transition through five distinct one-hot states. When the sequence 1011 is detected, the module asserts the detected signal for one clock cycle and sets the state vector to the final state. Because the detector is overlapping, a subsequent 0 after a successful detection must transition the FSM directly to the state representing a received 10.

Positive-edge triggered clock clk and active-low asynchronous reset rst_n govern the timing. On reset, the FSM must return to the initial state (5'b00001) and detected must be 0.

Worked Trace: • Cycle 1: rst_n=0, d=0 → state_out=5'b00001, detected=0 (Reset to IDLE) • Cycle 2: rst_n=1, d=1 → state_out=5'b00010, detected=0 (Received 1) • Cycle 3: rst_n=1, d=0 → state_out=5'b00100, detected=0 (Received 10) • Cycle 4: rst_n=1, d=1 → state_out=5'b01000, detected=0 (Received 101) • Cycle 5: rst_n=1, d=1 → state_out=5'b10000, detected=1 (Received 1011) • Cycle 6: rst_n=1, d=0 → state_out=5'b00100, detected=0 (Overlapping 10)

flowchart LR
    RESET(( )) -->|reset| IDLE
    IDLE((IDLE)) -->|d=1| S1
    IDLE -->|d=0| IDLE
    S1((S1)) -->|d=0| S10
    S1 -->|d=1| S1
    S10((S10)) -->|d=1| S101
    S10 -->|d=0| IDLE
    S101((S101)) -->|d=1| S1011
    S101 -->|d=0| S10
    S1011(["S1011 ★"]):::out -->|d=0| S10
    S1011 -->|d=1| S1
    classDef out fill:#6C5CE7,stroke:#5B4FE8,color:#fff

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; resets state to 5'b00001 | | d | input | 1 | Serial data input | | detected | output | 1 | Asserted high when sequence 1011 is detected | | state_out | output | 5 | Current one-hot state vector |

Constraints

• The FSM must be implemented using exactly 5 states.
• The state_out vector must always contain exactly one high bit (one-hot encoding).
• The reset state must be 5'b00001.
• Sequence detection must support overlapping patterns.
• The output detected must be combinationally derived from the current state or updated synchronously with the state transition.

Topics

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