Serial Adder Mealy Machine
Data transmission across low-pin-count interfaces often requires arithmetic operations to be performed bit-by-bit sequentially rather than in parallel. A serial adder computes the sum of two multi-bit numbers by processing one pair of bits per clock cycle, starting from the least significant bit.
The module reads input bits a and b and immediately produces the sum bit. The carry out of the current addition must be stored as the state for the next cycle's addition. Because the output depends on both the current state (the stored carry) and the current inputs, this must be implemented as a Mealy machine.
The design is synchronised to the positive edge of clk. It uses an asynchronous, active-low reset rst_n. On reset, the state becomes 0 (no carry) and the output sum reflects a ^ b immediately.
Cycle 1: rst_n=0 → state=0, a=0, b=0 → sum=0 Cycle 2: rst_n=1, a=1, b=1 → state=0 (carry=0), sum=0, next_state=1 Cycle 3: rst_n=1, a=0, b=1 → state=1 (carry=1), sum=0, next_state=1 Cycle 4: rst_n=1, a=0, b=0 → state=1 (carry=1), sum=1, next_state=0
flowchart LR
RESET(( )) -->|reset| S0
S0((S0: Carry 0)) -->|a=0,b=0 / sum=0| S0
S0 -->|a=0,b=1 or a=1,b=0 / sum=1| S0
S0 -->|a=1,b=1 / sum=0| S1
S1((S1: Carry 1)) -->|a=0,b=0 / sum=1| S0
S1 -->|a=0,b=1 or a=1,b=0 / sum=0| S1
S1 -->|a=1,b=1 / sum=1| S1{ "signal": [
{ "name": "clk", "wave": "p...." },
{ "name": "rst_n", "wave": "01..." },
{ "name": "a", "wave": "0100." },
{ "name": "b", "wave": "0110." },
{},
{ "name": "state", "wave": "=.=.=.=.=.", "data": ["0", "0", "1", "1", "0"] },
{ "name": "sum", "wave": "0.0.0.1.0." }
], "head": { "text": "Serial addition showing carry propagation." } }| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n| input | 1 | Asynchronous active-low reset; internal carry state goes to 0 | | a | input | 1 | First operand bit | | b | input | 1 | Second operand bit | | sum | output | 1 | Combinational sum output (Mealy) |
Constraints
summust be a combinational output reflecting the immediate sum ofa,b, and the current state.- The internal state (carry) must update on the positive edge of
clk. rst_nis asynchronous and active-low.- On reset, the internal carry state must become 0.
Topics
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