Valid and Ready Handshake Receiver
Data streaming interfaces in modern SoCs rely on a two-way handshake protocol to transfer data safely across clock domains or between modules with varying processing speeds. The receiver must explicitly signal its ability to accept incoming data, preventing the transmitter from overflowing the receiver's internal buffers.
This module acts as a handshake receiver. It monitors an incoming valid signal and an 8-bit data_in bus from an upstream transmitter. The module generates a ready signal to indicate it can accept data. A successful data transfer, known as a beat, occurs precisely on the rising clock edge where both valid and ready are asserted. To simulate downstream backpressure, an external pause signal is provided. When pause is asserted, the receiver must immediately deassert ready, preventing any new data from being accepted. The module captures accepted data into an 8-bit data_out register and maintains an 8-bit beat_count tracking the total number of successful transfers.
The module operates on the positive edge of clk and uses an asynchronous, active-low reset rst_n. On reset, data_out and beat_count clear to 0. The ready output is combinational; it must be high by default to accept data, but must be forced low whenever pause is high. The sequential outputs data_out and beat_count only update when a valid beat occurs. If no valid beat occurs on a given clock cycle, they must hold their previous values.
Worked Trace: Cycle 1: rst_n=0 → ready=1, data_out=8'h00, beat_count=8'h00 Cycle 2: rst_n=1, valid=1, pause=0, data_in=8'hAA → ready=1. Beat occurs. data_out=8'hAA, beat_count=8'h01 Cycle 3: valid=1, pause=1, data_in=8'hBB → ready=0. No beat. data_out=8'hAA (hold), beat_count=8'h01 (hold) Cycle 4: valid=0, pause=0, data_in=8'hBB → ready=1. No beat. data_out=8'hAA (hold), beat_count=8'h01 (hold) Cycle 5: valid=1, pause=0, data_in=8'hCC → ready=1. Beat occurs. data_out=8'hCC, beat_count=8'h02
{ "signal": [
{ "name": "clk", "wave": "p......." },
{ "name": "rst_n", "wave": "01......" },
{ "name": "valid", "wave": "01101100" },
{ "name": "pause", "wave": "00100010" },
{ "name": "data_in", "wave": "x======x", "data": ["AA", "BB", "BB", "CC", "DD", "EE"] },
{ "name": "ready", "wave": "11011101" },
{ "name": "data_out", "wave": "===..==.", "data": ["00", "00", "AA", "CC", "DD"] },
{ "name": "beat_count", "wave": "===..==.", "data": ["00", "00", "01", "02", "03"] }
], "head": { "text": "Cycle-by-cycle handshake protocol with backpressure." } }| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; sequential outputs go to 0 when asserted | | valid | input | 1 | Indicates data_in is valid | | data_in | input | 8 | Incoming data bus | | pause | input | 1 | Backpressure signal; forces ready low | | ready | output | 1 | Combinational output indicating receiver can accept data | | data_out | output | 8 | Registered output storing the last accepted data byte | | beat_count | output | 8 | Registered counter tracking the number of successful beats |
Constraints
- The
readyoutput must be evaluated combinationally and respond immediately to changes inpause. - A successful beat only occurs when
valid == 1andready == 1on the rising edge ofclk. data_outandbeat_countmust hold their previous values if a beat does not occur.beat_countmust wrap around to 0 naturally upon overflowing its 8-bit width.- The reset is asynchronous and active-low.
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