Arbiter FSM with Fixed Priority
Shared resources like memory controllers and system buses require arbitration to prevent multiple masters from driving data simultaneously. A fixed-priority arbiter resolves conflicts when multiple requestors demand access at the exact same time, ensuring deterministic system behaviour.
The solution module receives access requests from two agents, A and B. It grants access to one agent at a time. If both agents request access while the arbiter is idle, agent A receives the grant due to its higher fixed priority. Once an agent receives the grant, it retains ownership of the resource until it drops its request. The arbiter is non-preemptive; if agent B holds the grant, agent A cannot steal it, even if agent A asserts its request. When the current owner drops its request, the arbiter can immediately grant access to a pending request on the next clock cycle without passing through an idle state.
The module operates on a positive-edge triggered clock clk and an active-low synchronous reset rst_n. On reset, both grants are driven to 0 and the FSM enters the IDLE state. Outputs must be registered (Moore machine configuration) and reflect the current state of the FSM, meaning there is a one-cycle delay from a request being evaluated to the grant being asserted.
Cycle-by-cycle trace for simultaneous requests and non-preemption: • Cycle 1: rst_n=0 → state=IDLE, gnt_a=0, gnt_b=0 • Cycle 2: rst_n=1, req_a=1, req_b=1 → priority A wins, state goes to GRANT_A • Cycle 3: gnt_a=1, gnt_b=0 → state=GRANT_A. Both still requesting • Cycle 4: req_a=0, req_b=1 → A drops request, state transitions to GRANT_B • Cycle 5: gnt_a=0, gnt_b=1 → state=GRANT_B. A requests again, but B holds grant (non-preemptive) • Cycle 6: req_a=1, req_b=0 → B drops request, state transitions to GRANT_A • Cycle 7: gnt_a=1, gnt_b=0 → state=GRANT_A. A drops request, state transitions to IDLE • Cycle 8: gnt_a=0, gnt_b=0 → state=IDLE
flowchart LR
RESET(( )) -->|reset| IDLE
IDLE((IDLE)) -->|req_a=1| GRANT_A
IDLE -->|req_a=0, req_b=1| GRANT_B
IDLE -->|req_a=0, req_b=0| IDLE
GRANT_A(["GRANT_A ★"]):::out -->|req_a=1| GRANT_A
GRANT_A -->|req_a=0, req_b=1| GRANT_B
GRANT_A -->|req_a=0, req_b=0| IDLE
GRANT_B(["GRANT_B ★"]):::out -->|req_b=1| GRANT_B
GRANT_B -->|req_b=0, req_a=1| GRANT_A
GRANT_B -->|req_b=0, req_a=0| IDLE
classDef out fill:#6C5CE7,stroke:#5B4FE8,color:#fff{ "signal": [
{ "name": "clk", "wave": "p......." },
{ "name": "rst_n", "wave": "01......" },
{ "name": "req_a", "wave": "01.01.0." },
{ "name": "req_b", "wave": "01..0..." },
{},
{ "name": "gnt_a", "wave": "0.1.0.10" },
{ "name": "gnt_b", "wave": "0...1.0." }
], "head": { "text": "Arbiter grants priority to A, then non-preemptively allows B." } }| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Synchronous active-low reset; FSM goes to IDLE and grants go to 0 | | req_a | input | 1 | Request from agent A | | req_b | input | 1 | Request from agent B | | gnt_a | output | 1 | Grant for agent A; 1 when FSM is in GRANT_A state | | gnt_b | output | 1 | Grant for agent B; 1 when FSM is in GRANT_B state |
Constraints
- The reset must be synchronous and active-low.
- The FSM must be implemented as a Moore machine (outputs depend only on the current state).
- If both requests arrive in the IDLE state, agent A must receive the grant.
- The arbiter must be non-preemptive; an agent retains its grant as long as its request remains high, regardless of the other agent.
- The arbiter must be capable of handing off the grant directly from agent A to agent B (and vice versa) without passing through the IDLE state.
Topics
Solve this problem
Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.