Three Process Moore FSM Template

Hardware designers rely on consistent state machine templates to avoid race conditions, simplify timing analysis, and ensure readability. The three-process Moore machine is an industry-standard pattern that strictly separates the sequential state register, the combinational next-state decoding, and the combinational output decoding.

This module acts as a simple cyclical counter governed by a state machine. It has four states: S0, S1, S2, and S3. When the enable signal is asserted, the machine advances to the next state in the cycle (S0 to S1, S1 to S2, S2 to S3, S3 to S0). When the enable signal is de-asserted, the machine remains in its current state. The output is purely dependent on the current state, outputting 0 for S0, 1 for S1, 2 for S2, and 3 for S3.

The module is triggered on the positive edge of clk and uses an asynchronous active-low reset rst_n. On reset, the FSM enters S0 and the output goes to 0. The output logic must be combinational and based solely on the current state.

Cycle 1: rst_n=0 → state=S0, count=0 Cycle 2: rst_n=1, en=1 → state=S1, count=1 Cycle 3: en=1 → state=S2, count=2 Cycle 4: en=0 → state=S2, count=2 (hold) Cycle 5: en=1 → state=S3, count=3 Cycle 6: en=1 → state=S0, count=0 Cycle 7: en=1 → state=S1, count=1 Cycle 8: en=1 → state=S2, count=2

flowchart LR
    RESET(( )) -->|reset| S0
    S0(["S0 (0)"]) -->|en=1| S1
    S0 -->|en=0| S0
    S1(["S1 (1)"]) -->|en=1| S2
    S1 -->|en=0| S1
    S2(["S2 (2)"]) -->|en=1| S3
    S2 -->|en=0| S2
    S3(["S3 (3)"]):::out -->|en=1| S0
    S3 -->|en=0| S3
    classDef out fill:#6C5CE7,stroke:#5B4FE8,color:#fff

{ "signal": [
  { "name": "clk",   "wave": "p......." },
  { "name": "rst_n", "wave": "01......" },
  { "name": "en",    "wave": "x1101111" },
  {},
  { "name": "count", "wave": "========", "data": ["0","1","2","2","3","0","1","2"] }
], "head": { "text": "Cycle-by-cycle FSM behavior matching the worked trace." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n| input | 1 | Asynchronous active-low reset; FSM enters S0 when asserted | | en | input | 1 | Enable signal; FSM advances to next state on posedge clk when 1 | | count| output | 2 | Current count value corresponding to the FSM state; combinational |

Constraints

• Clock edge must be posedge and reset must be asynchronous negedge.
• The FSM logic must be separated into exactly three blocks: one sequential block for the state register, one combinational block for next-state logic, and one combinational block for output logic.
• The count output must strictly depend on the current state.
• When en is 0, the FSM must maintain its current state and output.

Topics

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