Sequence Detector: 101
Design a Moore finite state machine that detects the bit sequence 101 on a serial input x.
Output z is asserted to 1 for exactly one clock cycle when the last three received bits are 1, 0, 1 in order.
State Encoding
| State | Meaning | z | |-------|----------------|---| | S0 | Idle | 0 | | S1 | Received "1" | 0 | | S2 | Received "10" | 0 | | S3 | Received "101" | 1 |
Transitions
| Current | x=0 | x=1 | |---------|-----|-----| | S0 | S0 | S1 | | S1 | S2 | S1 | | S2 | S0 | S3 | | S3 | S2 | S1 |
After detection (S3), the FSM checks for overlapping sequences. If x=0, suffix "10" matches a prefix of "101" so it returns to S2. If x=1, suffix "1" matches so it goes to S1.
FSMs are the backbone of protocol controllers, parsers, and CPU control units.
Constraints
- Moore machine — output
zdepends only on current state, notx - Synchronous active-high reset returns FSM to S0 with z=0
- Overlapping sequences allowed (after detection, transition correctly)
- Use an
alwaysblock for state register and a separate one for next-state logic - Enumerate your states clearly (parameter or localparam)
Topics
Solve this problem
Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
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