Zero-Latency Sequence Detector (Mealy FSM)

High-speed serial links rely on pattern matchers to identify frame boundaries without introducing unnecessary pipeline delays. A zero-latency sequence detector flags a specific bit pattern the exact moment the final bit arrives, allowing downstream logic to act immediately rather than waiting for the next clock cycle.

The module continuously monitors a serial input stream on din. It searches for the overlapping bit sequence 101. When the final 1 of the sequence is present on the input, the output found asserts immediately in the same clock cycle. The output is purely combinational and depends on both the current state of the machine and the current input value.

• Clock edge: posedge
• Reset type: Asynchronous
• Reset polarity: Active-low
• Output values on reset: The FSM returns to its initial state, and found evaluates to 0.
• Priority rules: If rst_n is asserted, it overrides any data on din, forcing found to 0 immediately.

Worked Trace

Cycle 1: rst_n=0, din=0 → state=S0, found=0
Cycle 2: rst_n=1, din=1 → state=S1, found=0
Cycle 3: rst_n=1, din=0 → state=S10, found=0
Cycle 4: rst_n=1, din=1 → state=S1, found=1 (Sequence 101 completed)
Cycle 5: rst_n=1, din=0 → state=S10, found=0
Cycle 6: rst_n=1, din=1 → state=S1, found=1 (Overlapping 101 completed)
Cycle 7: rst_n=1, din=0 → state=S10, found=0

State Diagram

flowchart LR
    RESET(( )) -->|reset| S0
    S0((S0)) -->|din=1 / found=0| S1
    S0 -->|din=0 / found=0| S0
    S1((S1)) -->|din=0 / found=0| S10
    S1 -->|din=1 / found=0| S1
    S10(["S10 ★"]):::out -->|din=1 / found=1| S1
    S10 -->|din=0 / found=0| S0
    classDef out fill:#6C5CE7,stroke:#5B4FE8,color:#fff

Timing Diagram

{ "signal": [
  { "name": "clk",   "wave": "p......" },
  { "name": "rst_n", "wave": "01....." },
  { "name": "din",   "wave": "0101010" },
  {},
  { "name": "found", "wave": "0..1010" }
], "head": { "text": "Mealy machine detects overlapping 101 sequence with zero latency." } }

Port Table

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n| input | 1 | Asynchronous active-low reset; state returns to initial, found goes to 0 | | din | input | 1 | Serial data input | | found| output | 1 | Combinational output; 1 when 101 is detected, 0 otherwise |

Constraints

• Clock edge is posedge clk and reset is asynchronous active-low.
• Output found must evaluate to 0 when rst_n is asserted.
• The FSM must support overlapping sequences.
• Output found must be purely combinational. Do not register the found output.

Topics

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