Traffic Light Controller with Timer

Traffic intersections rely on robust state machines to manage traffic flow safely. Embedding countdown logic directly into state variables creates massive, unreadable state machines with hundreds of states. Best practice dictates separating the control logic (the FSM) from the timing logic (an external countdown timer).

The module coordinates a standard three-color traffic light cycle: Red, Green, Yellow, and back to Red. It interfaces with an external timer module to control the duration of each color. When the FSM enters a new state, it asserts a start signal for exactly one clock cycle. It then holds its current color output until the external timer asserts its done signal, at which point the FSM advances to the next color and issues a new start signal.

The circuit is driven by a positive-edge triggered clock and an asynchronous active-low reset. Upon reset, the FSM must enter the RED state and immediately assert the timer start signal to kick off the initial countdown. If the timer done signal is asserted on the exact cycle the reset is released, it must be ignored until the next clock cycle.

Worked Trace

Cycle 1: rst_n=0 → state=RED, light_state=00, timer_start=1 Cycle 2: rst_n=1, timer_done=0 → state=RED, light_state=00, timer_start=0 Cycle 3: timer_done=1 → state=GREEN, light_state=01, timer_start=1 Cycle 4: timer_done=0 → state=GREEN, light_state=01, timer_start=0 Cycle 5: timer_done=1 → state=YELLOW, light_state=10, timer_start=1

Diagram

flowchart LR
    RESET(( )) -->|reset| RED
    RED((RED 00)) -->|timer_done=1| GREEN
    RED -->|timer_done=0| RED
    GREEN((GREEN 01)) -->|timer_done=1| YELLOW
    GREEN -->|timer_done=0| GREEN
    YELLOW((YELLOW 10)) -->|timer_done=1| RED
    YELLOW -->|timer_done=0| YELLOW

Port Table

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; resets state to RED and asserts timer_start | | timer_done | input | 1 | Asserted by external timer when the wait period completes | | timer_start | output | 1 | Asserts for exactly one cycle when entering a new state or upon reset | | light_state | output | 2 | Current traffic light color (00=RED, 01=GREEN, 10=YELLOW) |

Constraints

• Clock is positive-edge triggered.
• Reset is asynchronous and active-low.
• Output light_state must be 2'b00 (RED) on reset.
• Output timer_start must be 1'b1 when reset is active, and for exactly one cycle after entering any new state.
• State transitions must occur exactly when timer_done is 1'b1.
• If timer_done is asserted during reset, it must be ignored until reset is released.
• State encoding must strictly follow: RED = 2'b00, GREEN = 2'b01, YELLOW = 2'b10.

Topics

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