Overlapping Sequence Detector Testbench

Verification suites rely on directed tests to hit specific edge cases that constrained random testing might miss. When verifying pattern recognition hardware, designers often incorrectly reset their state machines after a match, causing the circuit to miss overlapping sequences. A robust testbench must explicitly target this vulnerability by feeding a bitstream that contains overlaps and actively checking the detector's response.

Design a verification checker that drives a sequence detector and verifies its output. Your module will act as a standalone testbench component. It must generate an exact 8-bit serial bitstream (10101000) designed to test overlapping 1010 patterns. Alongside driving the stimulus, it must monitor the response from the Device Under Test (DUT). If the DUT fails to assert a match when expected, or asserts a match when it shouldn't, your module must flag an error. After outputting the 8th bit, it must assert a done flag to terminate the test.

• Clock edge: posedge clk
• Reset: Asynchronous active-low rst_n. When rst_n is 0, all outputs must be 0.
• On the first posedge clk after rst_n goes high, output the first bit of the test sequence 10101000 on seq_out. Advance one bit per cycle.
• The expected match signal for this exact sequence is 1 on the 4th bit and 6th bit, and 0 otherwise.
• On every posedge clk while the sequence is active, evaluate the dut_match input. If it does not equal the expected match value for the bit *currently driven* on seq_out, assert error to 1 on the next clock cycle.
• error is sticky: once asserted, it remains 1 until reset.
• done must assert to 1 on the cycle the 8th bit is driven and remain 1. seq_out should remain 0 after the 8th bit.

Cycle 1: rst_n=0, dut_match=0 → seq_out=0, error=0, done=0 Cycle 2: rst_n=1, dut_match=0 → seq_out=1, error=0, done=0 (Bit 1, expected match=0) Cycle 3: rst_n=1, dut_match=0 → seq_out=0, error=0, done=0 (Bit 2, expected match=0) Cycle 4: rst_n=1, dut_match=0 → seq_out=1, error=0, done=0 (Bit 3, expected match=0) Cycle 5: rst_n=1, dut_match=1 → seq_out=0, error=0, done=0 (Bit 4, expected match=1. DUT is correct) Cycle 6: rst_n=1, dut_match=0 → seq_out=1, error=0, done=0 (Bit 5, expected match=0) Cycle 7: rst_n=1, dut_match=0 → seq_out=0, error=0, done=0 (Bit 6, expected match=1. DUT MISSED the overlap!) Cycle 8: rst_n=1, dut_match=0 → seq_out=0, error=1, done=0 (Bit 7, expected match=0. Error asserted due to Cycle 7 mismatch) Cycle 9: rst_n=1, dut_match=0 → seq_out=0, error=1, done=1 (Bit 8, test complete)

{ "signal": [
  { "name": "clk",       "wave": "p........." },
  { "name": "rst_n",     "wave": "01........" },
  { "name": "seq_out",   "wave": "010101000.", "data": [] },
  { "name": "dut_match", "wave": "0...10000.", "data": [] },
  { "name": "error",     "wave": "0......1..", "data": [] },
  { "name": "done",      "wave": "0.......1.", "data": [] }
], "head": { "text": "DUT correctly identifies first pattern but misses the overlap." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; all outputs go to 0 | | dut_match | input | 1 | Match signal evaluated from the Device Under Test | | seq_out | output | 1 | Test sequence stimulus bit | | error | output | 1 | Asserts to 1 if dut_match is incorrect; sticky | | done | output | 1 | Test completion flag; asserts on 8th bit and holds |

Constraints

• Module must output exactly 10101000 starting from the first cycle after reset.
• The expected match signal for this sequence is 1 on the 4th bit and 6th bit, and 0 otherwise.
• error must be updated on the posedge clk immediately following a cycle where dut_match does not equal the expected match for that cycle's seq_out bit.
• error is sticky: once asserted, it remains 1 until reset.
• done must assert to 1 on the 8th bit of the sequence and remain 1.
• Once the 8-bit sequence is complete, ignore further dut_match inputs until the next reset.

Topics

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