Two Stage Datapath
High-speed digital signal processing often requires breaking complex arithmetic into smaller, registered stages to meet timing constraints. By inserting pipeline registers between operations, the combinational logic depth is reduced, allowing the entire system to run at a higher clock frequency.
The datapath takes two 8-bit data inputs and a 3-bit shift amount. In the first stage, the two 8-bit inputs are added together. In the second stage, the resulting sum is logically shifted left by the specified shift amount to produce the final output. Crucially, the shift amount must also be delayed by one clock cycle so that the correct shift amount is applied to the corresponding sum.
- Clock edge: posedge
clk - Reset type: asynchronous
- Reset polarity: active-low (
rst_n) - On reset, all internal pipeline registers and the output
d_outmust evaluate to 0.
Cycle 1: rst_n=0 → d_out=0, internal registers=0 Cycle 2: rst_n=1, d_in_a=2, d_in_b=3, d_in_shift=1 → Stage 1 computes sum=5 and stores shift=1. d_out=0 Cycle 3: d_in_a=4, d_in_b=4, d_in_shift=2 → Stage 1 computes sum=8 and stores shift=2. Stage 2 computes 5 << 1. d_out=10 Cycle 4: d_in_a=0, d_in_b=0, d_in_shift=0 → Stage 1 computes sum=0 and stores shift=0. Stage 2 computes 8 << 2. d_out=32
{ "signal": [
{ "name": "clk", "wave": "p......" },
{ "name": "rst_n", "wave": "01....." },
{ "name": "d_in_a", "wave": "x=.=.x.", "data": ["2", "4"] },
{ "name": "d_in_b", "wave": "x=.=.x.", "data": ["3", "4"] },
{ "name": "d_in_shift", "wave": "x=.=.x.", "data": ["1", "2"] },
{},
{ "name": "d_out", "wave": "0..=.=.", "data": ["10", "32"] }
], "head": { "text": "Pipeline execution showing the two-cycle latency from inputs to d_out." } }| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; all registers go to 0 | | d_in_a | input | 8 | First operand for the addition stage | | d_in_b | input | 8 | Second operand for the addition stage | | d_in_shift | input | 3 | Amount to left-shift the sum in the second stage | | d_out | output | 8 | Final registered output of the datapath |
Constraints
- The addition in the first stage must silently discard any overflow beyond 8 bits.
- The shift in the second stage must be a logical left shift.
- The output
d_outmust be registered; it cannot be a combinational output driven directly by the shift logic. - The
d_in_shiftsignal must be pipelined (registered) in the first stage so it aligns with the delayed sum in the second stage.
Topics
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