Two Stage Datapath

Putting a register in the middle of a long calculation halves the logic between flip-flops, so the clock can run faster. The cost is one extra cycle of latency.

The datapath takes two 8-bit data inputs and a 3-bit shift amount. In the first stage, the two 8-bit inputs are added together. In the second stage, the resulting sum is logically shifted left by the specified shift amount to produce the final output. Crucially, the shift amount must also be delayed by one clock cycle so that the correct shift amount is applied to the corresponding sum.

• Clock edge: posedge clk
• Reset type: asynchronous
• Reset polarity: active-low (rst_n)
• On reset, all internal pipeline registers and the output d_out must evaluate to 0.

Cycle 1: rst_n=0 → d_out=0, internal registers=0
Cycle 2: rst_n=1, d_in_a=2, d_in_b=3, d_in_shift=1 → Stage 1 computes sum=5 and stores shift=1. d_out=0
Cycle 3: d_in_a=4, d_in_b=4, d_in_shift=2 → Stage 1 computes sum=8 and stores shift=2. Stage 2 computes 5 << 1. d_out=10
Cycle 4: d_in_a=0, d_in_b=0, d_in_shift=0 → Stage 1 computes sum=0 and stores shift=0. Stage 2 computes 8 << 2. d_out=32

• The addition in the first stage must silently discard any overflow beyond 8 bits.
• The shift in the second stage must be a logical left shift.
• The output d_out must be registered; it cannot be a combinational output driven directly by the shift logic.
• The d_in_shift signal must be pipelined (registered) in the first stage so it aligns with the delayed sum in the second stage.