Variable Swap Without Temporary Storage

In software, swapping two values needs a temporary. With nonblocking assignments every right-hand side is read before any register updates, so two registers can swap in one clock with no temporary at all.

The solution module maintains two 8-bit registers. New data is latched from the input ports when the load signal is asserted. When the swap signal is active, the values held in the two internal registers are exchanged. The current values of these registers are continuously driven to the output ports.

The module is driven by a positive-edge triggered clock clk and a synchronous active-high reset rst. On reset, both a_out and b_out initialize to 8'h00. The rst signal has the highest priority. If rst is not asserted, load has priority over swap. If both load and swap are asserted simultaneously, the module must load the new inputs and ignore the swap command. If neither load nor swap is asserted, the registers hold their current values. All outputs are registered.

Cycle 1: rst=1, load=0, swap=0 → a_out=0, b_out=0 (Reset applied)
Cycle 2: rst=0, load=1, a_in=5, b_in=10, swap=0 → a_out=5, b_out=10 (Load values)
Cycle 3: rst=0, load=0, swap=1 → a_out=10, b_out=5 (Swap values)
Cycle 4: rst=0, load=0, swap=1 → a_out=5, b_out=10 (Swap again)
Cycle 5: rst=0, load=1, swap=1, a_in=7, b_in=8 → a_out=7, b_out=8 (Load overrides swap)
Cycle 6: rst=0, load=0, swap=0 → a_out=7, b_out=8 (Hold values)

• The design must trigger on the positive edge of clk.
• The rst signal is synchronous and active-high.
• Both a_out and b_out must reset to 8'h00.
• Priority order: rst > load > swap.
• Do not declare any internal temporary registers to facilitate the swap; use concurrent nonblocking assignments.