Variable Swap Without Temporary Storage

Software algorithms typically require a temporary variable to swap two values. In hardware design, nonblocking assignments evaluate the right-hand side of all statements concurrently before updating any left-hand side. This allows two registers to exchange their contents in a single clock cycle without requiring intermediate storage.

The solution module maintains two 8-bit registers. New data is latched from the input ports when the load signal is asserted. When the swap signal is active, the values held in the two internal registers are exchanged. The current values of these registers are continuously driven to the output ports.

The module is driven by a positive-edge triggered clock clk and a synchronous active-high reset rst. On reset, both a_out and b_out initialize to 8'h00. The rst signal has the highest priority. If rst is not asserted, load has priority over swap. If both load and swap are asserted simultaneously, the module must load the new inputs and ignore the swap command. If neither load nor swap is asserted, the registers hold their current values. All outputs are registered.

Cycle 1: rst=1, load=0, swap=0 → a_out=0, b_out=0 (Reset applied) Cycle 2: rst=0, load=1, a_in=5, b_in=10, swap=0 → a_out=5, b_out=10 (Load values) Cycle 3: rst=0, load=0, swap=1 → a_out=10, b_out=5 (Swap values) Cycle 4: rst=0, load=0, swap=1 → a_out=5, b_out=10 (Swap again) Cycle 5: rst=0, load=1, swap=1, a_in=7, b_in=8 → a_out=7, b_out=8 (Load overrides swap) Cycle 6: rst=0, load=0, swap=0 → a_out=7, b_out=8 (Hold values)

{ "signal": [
  { "name": "clk",   "wave": "p......" },
  { "name": "rst",   "wave": "10....." },
  { "name": "load",  "wave": "010010." },
  { "name": "swap",  "wave": "001110." },
  { "name": "a_in",  "wave": "x=xx=x.", "data": ["5", "7"] },
  { "name": "b_in",  "wave": "x=xx=x.", "data": ["10", "8"] },
  {},
  { "name": "a_out", "wave": "=.====.", "data": ["0", "5", "10", "5", "7", "7"] },
  { "name": "b_out", "wave": "=.====.", "data": ["0", "10", "5", "10", "8", "8"] }
], "head": { "text": "Cycle-by-cycle trace showing load, swap, and priority rules." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst | input | 1 | Synchronous active-high reset; clears outputs to 8'h00 | | load | input | 1 | Active-high enable to load a_in and b_in into the registers | | swap | input | 1 | Active-high enable to swap the current values of the registers | | a_in | input | 8 | Input data for register A | | b_in | input | 8 | Input data for register B | | a_out| output | 8 | Current value of register A | | b_out| output | 8 | Current value of register B |

Constraints

• The design must trigger on the positive edge of clk.
• The rst signal is synchronous and active-high.
• Both a_out and b_out must reset to 8'h00.
• Priority order: rst > load > swap.
• Do not declare any internal temporary registers to facilitate the swap; use concurrent nonblocking assignments.

Topics

Related problems

• Basic D Flip FlopEasy
• Debug: Missing Edge in Sensitivity ListMedium
• Read After Write Hazard DetectionEasy
• Parameterized Interface with ModportsHard
• Struct Array PipelineHard
• T Flip Flop from D Flip Flop TemplateEasy
• Recursive Generate Reduction TreeHard
• Four Stage Shift RegisterEasy