Valid Data Propagation
Data that takes two cycles to compute needs its valid flag delayed by the same two cycles. Otherwise downstream logic takes garbage for a result.
The module delays an 8-bit data bus and its associated valid signal by exactly two clock cycles. The output data and output valid signal must unconditionally reflect the inputs from two clock cycles prior.
The circuit operates on the positive edge of clk. An asynchronous, active-low reset rst_n clears all pipeline stages, forcing both the data and valid outputs to zero.
Cycle 1: rst_n=0 → valid_out=0, data_out=8'h00
Cycle 2: rst_n=1, valid_in=1, data_in=8'hAA → valid_out=0, data_out=8'h00
Cycle 3: valid_in=0, data_in=8'hBB → valid_out=0, data_out=8'h00
Cycle 4: valid_in=1, data_in=8'hCC → valid_out=1, data_out=8'hAA
Cycle 5: valid_in=0, data_in=8'h00 → valid_out=0, data_out=8'hBB
Cycle 6: valid_in=0, data_in=8'h00 → valid_out=1, data_out=8'hCC
| Signal | Direction | Width | Description |
|---|---|---|---|
clk |
input | 1 | Positive-edge triggered clock |
rst_n |
input | 1 | Asynchronous active-low reset; all outputs and internal registers go to 0 when asserted |
valid_in |
input | 1 | Input valid strobe |
data_in |
input | 8 | Input data bus |
valid_out |
output | 1 | Output valid strobe; reflects valid_in from two cycles prior |
data_out |
output | 8 | Output data bus; reflects data_in from two cycles prior |
Constraints
- The circuit must trigger on the positive edge of
clk. - The reset must be asynchronous and active-low.
- All internal pipeline registers and outputs must reset to 0.
- Both
data_inandvalid_inmust be pipelined unconditionally; the data pipeline must shift every cycle regardless of the state ofvalid_in.
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