Synchronous Rising Edge Detector

Every digital protocol receiver needs a way to identify the start of a transaction, such as detecting the assertion of a chip select or the start bit of a UART frame.

This module monitors a continuous input signal and generates a single-cycle active-high pulse exactly when the input transitions from low to high. If the input remains high for multiple cycles, the output remains low after the initial pulse.

Timing and Reset Rules: • Clock edge: posedge clk • Reset type: asynchronous, active-low (rst_n) • Output on reset: pulse evaluates to 0 • The pulse output must be combinational, evaluating to 1 in the exact same cycle that din is high but was low in the previous cycle.

Worked Trace: Cycle 1: rst_n=0 → internal state=0, pulse=0 Cycle 2: rst_n=1, din=0 → internal state=0, pulse=0 Cycle 3: din=1 → internal state=0, pulse=1 Cycle 4: din=1 → internal state=1, pulse=0 Cycle 5: din=0 → internal state=1, pulse=0 Cycle 6: din=0 → internal state=0, pulse=0 Cycle 7: din=1 → internal state=0, pulse=1

{ "signal": [
  { "name": "clk",   "wave": "p......." },
  { "name": "rst_n", "wave": "01......" },
  { "name": "din",   "wave": "0.1..0.1" },
  {},
  { "name": "pulse", "wave": "0.10.0.1" }
], "head": { "text": "Combinational pulse asserts on the cycle din goes high." } }

Port Table:

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; internal state goes to 0 | | din | input | 1 | Synchronous input signal to be monitored | | pulse | output | 1 | Combinational active-high output asserting when din transitions to 1 |

Constraints

• Clock edge is posedge clk.
• Reset is asynchronous, active-low (negedge rst_n).
• The pulse output must be combinational, asserting in the exact same cycle that din transitions to 1.
• Do not use din in the sensitivity list of any always block.
• On reset, the internal state must be cleared to 0.

Topics

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