Basic D Flip Flop
The D flip-flop is where state begins: it copies its input on the clock edge and holds that value until the next edge.
The module transfers the value on its data input to its data output strictly on the active clock edge. Between active clock edges, the output remains unchanged regardless of what happens on the input.
The module is driven by a positive-edge triggered clock clk. It features an asynchronous, active-low reset rst_n. When rst_n is asserted (pulled to 0), the output q must immediately go to 0, regardless of the clock state. When rst_n is de-asserted (pulled to 1), q will capture the value of d on every positive edge of clk.
Cycle 1: rst_n=0, d=x → q=0 (asynchronous reset holds output at 0)
Cycle 2: rst_n=1, d=1 → q=1 (posedge clk captures d=1)
Cycle 3: rst_n=1, d=1 → q=1 (steady state)
Cycle 4: rst_n=1, d=0 → q=0 (posedge clk captures d=0)
Cycle 5: rst_n=1, d=0 → q=0 (steady state)
Cycle 6: rst_n=1, d=1 → q=1 (posedge clk captures d=1)
Cycle 7: rst_n=1, d=1 → q=1 (steady state)
| Signal | Direction | Width | Description |
|---|---|---|---|
clk |
input | 1 | Positive-edge triggered clock |
rst_n |
input | 1 | Asynchronous active-low reset; q goes to 0 when asserted |
d |
input | 1 | Data input |
q |
output | 1 | Registered data output; resets to 1'b0 |
Constraints
- Output
qmust be updated only on the positive edge ofclkor the negative edge ofrst_n. - Reset must be asynchronous and active-low.
- Output
qmust evaluate to 0 whenrst_nis 0. - You must use non-blocking assignments (
<=) for the sequential logic to pass strict linting rules.
Topics
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