Basic D Flip Flop

Every digital circuit relies on state elements to hold data across clock cycles and synchronize logic paths. The D flip-flop is the fundamental building block that captures a data input on a clock edge and holds it steady until the next edge.

The module transfers the value on its data input to its data output strictly on the active clock edge. Between active clock edges, the output remains unchanged regardless of what happens on the input.

The module is driven by a positive-edge triggered clock clk. It features an asynchronous, active-low reset rst_n. When rst_n is asserted (pulled to 0), the output q must immediately go to 0, regardless of the clock state. When rst_n is de-asserted (pulled to 1), q will capture the value of d on every positive edge of clk.

Cycle 1: rst_n=0, d=x → q=0 (asynchronous reset holds output at 0) Cycle 2: rst_n=1, d=1 → q=1 (posedge clk captures d=1) Cycle 3: rst_n=1, d=1 → q=1 (steady state) Cycle 4: rst_n=1, d=0 → q=0 (posedge clk captures d=0) Cycle 5: rst_n=1, d=0 → q=0 (steady state) Cycle 6: rst_n=1, d=1 → q=1 (posedge clk captures d=1) Cycle 7: rst_n=1, d=1 → q=1 (steady state)

{ "signal": [
  { "name": "clk",   "wave": "p......" },
  { "name": "rst_n", "wave": "01....." },
  { "name": "d",     "wave": "x1.0.1." },
  {},
  { "name": "q",     "wave": "0.1.0.1" }
], "head": { "text": "Basic D Flip-Flop with asynchronous active-low reset." } }

| Signal | Direction | Width | Description | |---------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; q goes to 0 when asserted | | d | input | 1 | Data input | | q | output | 1 | Registered data output; resets to 1'b0 |

Constraints

• Output q must be updated only on the positive edge of clk or the negative edge of rst_n.
• Reset must be asynchronous and active-low.
• Output q must evaluate to 0 when rst_n is 0.
• You must use non-blocking assignments (<=) for the sequential logic to pass strict linting rules.

Topics

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