Four Stage Shift Register
Delaying a signal by a fixed number of cycles is how parallel paths with different latencies get lined up again. Four flip-flops in a chain give four cycles.
A four-stage shift register accepts a serial input stream and passes it through four cascaded flip-flops. The output of the module is the input signal delayed by exactly four clock cycles. If the input goes high in cycle 1, the output will go high in cycle 5.
The circuit uses a positive-edge triggered clock. An asynchronous active-low reset clears all internal stages and the output to 0 immediately when asserted. When reset is de-asserted, the shift register captures the input on each rising clock edge and shifts the data forward one stage.
Cycle 1: rst_n=0 → q=0
Cycle 2: rst_n=1, d=1 → q=0 (data enters stage 1)
Cycle 3: rst_n=1, d=0 → q=0 (data enters stage 2)
Cycle 4: rst_n=1, d=0 → q=0 (data enters stage 3)
Cycle 5: rst_n=1, d=0 → q=1 (data enters stage 4, appears at output)
Cycle 6: rst_n=1, d=0 → q=0 (data shifts out)
| Signal | Direction | Width | Description |
|---|---|---|---|
clk |
input | 1 | Positive-edge triggered clock |
rst_n |
input | 1 | Asynchronous active-low reset; all outputs and internal stages go to 0 when asserted |
d |
input | 1 | Serial data input |
q |
output | 1 | Serial data output, delayed by four clock cycles; resets to 0 |
Constraints
- Clock is positive-edge triggered.
- Reset is asynchronous and active-low.
- Output
qmust be registered. - You must declare and instantiate four distinct register variables (for example
q0,q1,q2,q3) rather than a single 4-bit array to prove your understanding of concurrent assignments.
Topics
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