Debug: Blocking Assignment Race Condition
A two-stage pipeline delays d by two clock cycles, so q shows the value d had two cycles earlier.
Expected behaviour, reading q just before each rising edge:
| Cycle | d |
q |
|---|---|---|
| 1 | 1 | 0 |
| 2 | 0 | 0 |
| 3 | 0 | 1 |
| 4 | 0 | 0 |
What the simulation shows: q goes high in cycle 2, one cycle early. The pipeline behaves like a single register: the second stage copies the first stage's new value on the same edge.
The design below has one bug. Find it and fix it.
| Signal | Direction | Width | Description |
|---|---|---|---|
clk |
input | 1 | Clock, rising edge |
d |
input | 1 | Data in |
q |
output | 1 | d delayed by two cycles |
Constraints
- Keep the port list
clk,d,q. - Don't add pipeline stages or registers.
- Change at most 2 lines.
Topics
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