Debug: Blocking Assignment Race Condition
A two-stage pipeline delays the input data by two clock cycles to synchronize logic.
Expected behavior:
| Cycle | d | q | |-------|-----|-----| | 1 | 1 | 0 | | 2 | 0 | 0 | | 3 | 0 | 1 | | 4 | 0 | 0 |
Simulation shows q = 1 on Cycle 1 when d = 1. The output updates to the current value of the input on the exact same clock edge. The pipeline is simulating as a zero-cycle direct wire instead of a two-stage shift register. Inspect the RTL code and correct the fault.
Constraints
- The module must maintain the exact same port list:
clk,d, andq. - Do not add additional pipeline stages or registers.
- Only modify the assignment operators inside the sequential block.
Topics
Solve this problem
Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.