Time-Multiplexed Multiply-Accumulate
Four multiplications in one cycle need four multipliers. Doing one per cycle for four cycles needs one multiplier and a little control logic, which is the trade this problem is about.
This module computes the sum of four products: (d1 * c1) + (d2 * c2) + (d3 * c3) + (d4 * c4). Instead of computing this in a single clock cycle with four multipliers, it time-multiplexes a single 8-bit by 8-bit multiplier over four clock cycles. When start is asserted, the module begins the multiply-accumulate sequence. On the fourth cycle of computation, it asserts done and outputs the final 18-bit accumulated result.
Timing and Reset Rules:
- Clock edge:
posedge clk - Reset:
negedge rst_n(asynchronous, active-low) - On reset,
doneandresultmust be0. The internal accumulator and state must also reset. startis asserted for exactly one clock cycle. The inputsd1throughc4are guaranteed to remain stable for the entire 4-cycle computation.donemust be asserted for exactly one clock cycle when the final result is ready, simultaneously with the validresult.- The module must return to the idle state immediately after asserting
done, ready to accept a newstartpulse on the very next cycle.
Worked Trace (values just after each rising edge):
- Edge 1,
rst_n=0: IDLE,done=0,result=0. - Edge 2,
start=1: leaves IDLE. The four compute cycles begin. - Edge 3: accumulator =
d1*c1. - Edge 4: accumulator =
d1*c1 + d2*c2. - Edge 5: accumulator =
d1*c1 + d2*c2 + d3*c3. - Edge 6:
done=1,result= all four products summed. Back to IDLE. - Edge 7:
done=0,resultholds.
| Signal | Direction | Width | Description |
|---|---|---|---|
clk |
input | 1 | Positive-edge triggered clock |
rst_n |
input | 1 | Asynchronous active-low reset |
start |
input | 1 | 1-cycle pulse to begin computation |
d1, d2, d3, d4 |
input | 8 | Data inputs |
c1, c2, c3, c4 |
input | 8 | Coefficient inputs |
done |
output | 1 | 1-cycle pulse when computation is complete |
result |
output | 18 | Accumulated result, valid when done=1 |
Constraints
- Clock is positive-edge triggered; reset is asynchronous and active-low.
- All outputs and internal registers must be initialized to 0 on reset.
- You must use exactly one
*operator in your RTL. Instantiating multiple multipliers violates the core area-saving constraint of this problem. - The
resultoutput must be exactly 18 bits wide to prevent overflow. donemust assert for exactly one cycle.- The computation must take exactly 4 cycles from
starttodone.
Topics
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