T Flip Flop from D Flip Flop Template

Modern FPGA architectures standardise on D-type flip flops for their logic cells, omitting dedicated T-type (toggle) flip flops to save silicon area. Hardware engineers must synthesise toggle functionality using standard D flip flops paired with combinational feedback logic.

The circuit maintains its current state until the toggle enable signal is asserted. When enabled, the output state inverts on every active clock edge. This fundamental building block is heavily used in binary counters, clock dividers, and state machine design.

• Clock edge: posedge
• Reset type: asynchronous
• Reset polarity: active-low (rst_n)
• Output values on reset: q goes to 0
• Priority rules: rst_n assertion overrides the t input
• The output q must be registered

Cycle 1: rst_n=0, t=X → q=0 (reset) Cycle 2: rst_n=1, t=0 → q=0 (hold) Cycle 3: rst_n=1, t=1 → q=1 (toggle) Cycle 4: rst_n=1, t=1 → q=0 (toggle) Cycle 5: rst_n=1, t=0 → q=0 (hold) Cycle 6: rst_n=1, t=1 → q=1 (toggle) Cycle 7: rst_n=0, t=1 → q=0 (reset overrides toggle) Cycle 8: rst_n=1, t=0 → q=0 (hold)

{ "signal": [
  { "name": "clk",   "wave": "p......." },
  { "name": "rst_n", "wave": "01....01" },
  { "name": "t",     "wave": "x01.01.0" },
  {},
  { "name": "q",     "wave": "0.10.10." }
], "head": { "text": "Toggle behaviour with asynchronous reset." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; q goes to 0 when asserted | | t | input | 1 | Toggle enable; q inverts on posedge clk while t is 1 | | q | output | 1 | Registered output state |

Constraints

• Output q must be registered, updating only on the positive edge of clk or upon asynchronous reset.
• The reset signal rst_n is asynchronous and active-low.
• Output must initialise to 0 on reset.
• Reset assertion strictly overrides the t input.

Topics

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