JK Flip Flop Synthesis Verification

Legacy schematics and older digital design textbooks heavily feature JK flip-flops due to their versatility in building counters and state machines. However, modern standard cell libraries typically only provide D flip-flops. Synthesis tools like Yosys must map JK behavior into a standard D flip-flop preceded by multiplexers and combinational logic. A precise RTL implementation ensures the synthesizer can optimize this logic accurately into standard library cells.

A JK flip-flop updates its output state based on the values of the j and k inputs. When both inputs are low, the output holds its current value. When j is high and k is low, the output sets to 1. When k is high and j is low, the output clears to 0. When both inputs are high, the output toggles its state, inverting the previous value.

• Clock edge: posedge clk
• Reset type: asynchronous
• Reset polarity: active-low (rst_n)
• Output values on reset: q becomes 0 immediately when rst_n is 0
• Priority rules: Asynchronous reset takes highest priority; j and k inputs are only evaluated on the positive clock edge when rst_n is 1.

Cycle 1: rst_n=0 -> q=0 Cycle 2: rst_n=1, j=1, k=0 -> q=1 (Set) Cycle 3: rst_n=1, j=0, k=0 -> q=1 (Hold) Cycle 4: rst_n=1, j=0, k=1 -> q=0 (Reset) Cycle 5: rst_n=1, j=1, k=1 -> q=1 (Toggle) Cycle 6: rst_n=1, j=1, k=1 -> q=0 (Toggle)

{ "signal": [
  { "name": "clk",   "wave": "p......" },
  { "name": "rst_n", "wave": "01....." },
  { "name": "j",     "wave": "010011." },
  { "name": "k",     "wave": "000111." },
  {},
  { "name": "q",     "wave": "0.1.010" }
], "head": { "text": "Cycle-by-cycle evaluation of JK flip-flop behavior." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n| input | 1 | Asynchronous active-low reset; q goes to 0 when asserted | | j | input | 1 | Set/Toggle input; evaluated on posedge clk | | k | input | 1 | Reset/Toggle input; evaluated on posedge clk | | q | output | 1 | Registered output state; resets to 0 |

Constraints

• Output q must be registered on the positive edge of clk.
• Reset rst_n must be asynchronous and active-low.
• When rst_n is 0, q must immediately become 0 regardless of the clock.
• Both j and k being 1 must result in q inverting its previous state.

Topics

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