Debug: Missing Edge in Sensitivity List
An asynchronous reset initialises a register without waiting for a clock edge. This D flip-flop is meant to have an active-high asynchronous reset.
Expected behaviour:
- When
rstis 1,qbecomes 0 immediately, whether or not the clock is running. - When
rstis 0,qcapturesdon the rising edge ofclk.
What the simulation shows: with the clock held at 0 and q at 1, raising rst leaves q at 1. It only clears on the next rising edge of clk, which is a synchronous reset, not an asynchronous one.
The design below has one bug. Find it and fix it.
| Signal | Direction | Width | Description |
|---|---|---|---|
clk |
input | 1 | Clock, rising edge |
rst |
input | 1 | Asynchronous reset, active high |
d |
input | 1 | Data in |
q |
output | 1 | Registered data out |
Constraints
- The reset must stay active high and asynchronous.
- Keep the port list and signal names as they are.
- Change at most 1 line.
Topics
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