Debug: Missing Edge in Sensitivity List
An asynchronous reset ensures a sequential circuit initializes to a known state without waiting for an active clock edge. A standard D flip-flop with an active-high asynchronous reset evaluates the reset condition independently of the clock.
Expected behavior:
When rst is 1, the output q becomes 0 immediately. When rst is 0, the output q captures the value of d on the rising edge of clk.
Simulation shows a test failure when the clock is paused. The test asserts rst to 1 while clk is held at 0 and q is 1. The output q remains 1 instead of clearing to 0. The reset incorrectly waits for the next rising edge of clk before taking effect. Inspect the circuit and correct the fault.
Constraints
- The reset must be active-high and asynchronous.
- The module port list and signal names must not be changed.
Topics
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Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
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