Convert to always_ff
Legacy RTL codebases frequently use the generic always block for both combinational and sequential logic. SystemVerilog introduced specific blocks like always_ff to clearly express design intent, allowing synthesis tools and linters to enforce strict checks and prevent accidental latches.
The provided module is an 8-bit counter written using legacy Verilog syntax. It features a synchronous active-high reset, a data load function, and an increment enable. The logic works correctly, but the codebase is migrating to SystemVerilog standards. The task is to update the sequential block to use always_ff and verify that the module retains its exact functionality.
The counter operates on the positive edge of the clock. When the synchronous reset is asserted, the output clears to zero. If reset is de-asserted, the load signal takes priority over the enable signal. When load is high, the counter takes the value of the input data. When enable is high and load is low, the counter increments by one.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst | input | 1 | Synchronous active-high reset; clears count to 0 when asserted | | load | input | 1 | Load enable; loads data_in into count when high | | en | input | 1 | Count enable; increments count by 1 when high | | data_in | input | 8 | Data to load into the counter | | count | output | 8 | Current counter value; resets to 8'h00 |
Constraints
- The module must use
always_fffor all sequential logic - The
alwayskeyword must not be used without the_ffsuffix - The clock edge must be
posedge clk - The reset must be synchronous and active-high
- Priority must be strictly maintained:
rstoverridesload, which overridesen - The counter must wrap around to 8'h00 naturally upon reaching 8'hFF
Topics
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