Transparent Latch using always_latch

Clock gating cells and specific asynchronous bus protocols rely on level-sensitive latches to hold state during inactive clock phases. While standard synthesis tools flag latches as unintended bugs in combinational logic, hardware engineers must sometimes instantiate them intentionally.

The module acts as an 8-bit transparent D-latch with an asynchronous active-low reset. When the reset is asserted, the output clears to zero immediately. During normal operation, when the enable signal is high, the output transparently follows the data input. When the enable signal transitions low, the output holds the last observed data value regardless of subsequent changes on the data input.

Timing and Reset Rules:

• Trigger: Level-sensitive; no clock edge is used
• Reset type: Asynchronous
• Reset polarity: Active-low
• Output values on reset: q clears to 8'b00000000
• Priority rules: rst_n overrides en; if rst_n is low, the output is zero regardless of en or d

Worked Trace:

Step 1: rst_n=0, en=X, d=X → q=0 (Reset) Step 2: rst_n=1, en=1, d=170 → q=170 (Transparent) Step 3: rst_n=1, en=0, d=187 → q=170 (Hold) Step 4: rst_n=1, en=0, d=204 → q=170 (Hold) Step 5: rst_n=1, en=1, d=204 → q=204 (Transparent) Step 6: rst_n=0, en=0, d=204 → q=0 (Async Reset)

{ "signal": [
  { "name": "rst_n", "wave": "011110" },
  { "name": "en",    "wave": "x10010" },
  { "name": "d",     "wave": "x=====", "data": ["170", "187", "204", "204", "204"] },
  {},
  { "name": "q",     "wave": "0====0", "data": ["170", "170", "170", "204"] }
], "head": { "text": "Level-sensitive latch behavior with asynchronous reset." } }

Port Table:

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | d | input | 8 | Data input | | en | input | 1 | Active-high latch enable | | rst_n| input | 1 | Asynchronous active-low reset; clears q to 0 when asserted | | q | output | 8 | Latch output; resets to 8'b00000000 |

Constraints

• Output q must be explicitly modeled as a latch using the SystemVerilog always_latch block
• Reset is asynchronous and active-low
• When en is low and rst_n is high, q must hold its previous value
• No clock signal is provided; the logic must be entirely level-sensitive

Topics

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