Two Dimensional Array Register Verification
High-speed control pipelines often require small, extremely fast lookup tables or configuration registers. When memory arrays are very small, synthesizing them into discrete flip-flops rather than dedicated Block RAM (BRAM) minimizes routing delay and avoids the synchronous read latency inherent to BRAM macros.
The module acts as a 4-word by 8-bit register file. It has independent read and write ports. When the write enable signal is asserted, the data on the write data port is written to the specified write address. The read port continuously outputs the contents of the memory at the given read address, independent of the clock.
Timing and Reset Rules: • Clock edge: posedge clk • Reset type: asynchronous • Reset polarity: active-low rst_n • Reset behavior: All 4 memory locations must be explicitly cleared to 8'h00 when reset is asserted. • Write operation: Synchronous to posedge clk when we is 1. • Read operation: Combinational. The output rdata immediately reflects the contents of the array at raddr. • Priority rules: If raddr equals waddr while we is 1, the read data reflects the old value (read-before-write) because the read is combinational and the write is registered.
Worked Trace: Cycle 1: rst_n=0, we=0, waddr=0, wdata=0, raddr=0 → Array is cleared. rdata=0. Cycle 2: rst_n=1, we=1, waddr=1, wdata=165, raddr=1 → Array index 1 gets 165 at the clock edge. rdata=0 (old value). Cycle 3: rst_n=1, we=0, waddr=0, wdata=0, raddr=1 → Write disabled. rdata=165. Cycle 4: rst_n=1, we=1, waddr=2, wdata=60, raddr=2 → Array index 2 gets 60 at the clock edge. rdata=0. Cycle 5: rst_n=1, we=0, waddr=0, wdata=0, raddr=2 → Write disabled. rdata=60.
{ "signal": [
{ "name": "clk", "wave": "p...." },
{ "name": "rst_n", "wave": "01..." },
{ "name": "we", "wave": "01010" },
{ "name": "waddr", "wave": "=====", "data": ["0", "1", "0", "2", "0"] },
{ "name": "wdata", "wave": "=====", "data": ["0", "165", "0", "60", "0"] },
{ "name": "raddr", "wave": "=====", "data": ["0", "1", "1", "2", "2"] },
{},
{ "name": "rdata", "wave": "=====", "data": ["0", "0", "165", "0", "60"] }
], "head": { "text": "Cycle-by-cycle trace of reset, write, and combinational read operations." } }Port Table:
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; all memory locations clear to 0 | | we | input | 1 | Write enable; active high | | waddr | input | 2 | Write address indicating which of the 4 locations to update | | wdata | input | 8 | Write data to be written into the array | | raddr | input | 2 | Read address indicating which of the 4 locations to output | | rdata | output | 8 | Combinational read data output |
Constraints
- All 32 bits of the memory array must be explicitly reset to 0 when
rst_nis 0. - Reads must be strictly combinational (asynchronous read).
- Writes must be synchronous to the positive edge of
clk. - The synthesis tool will verify exactly 32 flip-flops are inferred.
Topics
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