D Flip-Flop
Design a synchronous D flip-flop with active-high reset in Verilog.
The flip-flop captures the value of input d on every rising edge of clk and holds it on output q until the next rising edge.
Behaviour
| reset | d | q after rising edge | |-------|---|---------------------| | 1 | x | 0 | | 0 | 0 | 0 | | 0 | 1 | 1 |
When reset = 1, output is forced to 0 on the next rising edge regardless of d (synchronous reset). When reset = 0, output follows d.
The D flip-flop is the fundamental building block of all sequential digital circuits — registers, counters, and state machines are all built from it.
Constraints
- Rising-edge triggered — use
always @(posedge clk) - Reset is synchronous and active-high
- Reset has priority over
d - Declare
qasreg - No combinational latches allowed
Topics
Solve this problem
Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
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