4-Bit Serial-In Shift Register
Design a 4-bit serial-in parallel-out (SIPO) shift register in Verilog.
On each rising clock edge the register shifts its contents left by one position and inserts the serial input si into the LSB.
Shift Operation
q <= {q[2:0], si}
This means: • q[3] receives the old q[2] • q[2] receives the old q[1] • q[1] receives the old q[0] • q[0] receives the new serial input si
Example — four consecutive shifts with si=1 starting from reset
| Cycle | si | q | |-------|----|------| | 0 | x | 0000 | | 1 | 1 | 0001 | | 2 | 1 | 0011 | | 3 | 1 | 0111 | | 4 | 1 | 1111 |
Shift registers are used for serial-to-parallel conversion, data buffering, and delay lines.
Constraints
- Synchronous active-high reset — clears all bits to 0
- Shift happens on every rising clock edge when reset is inactive
- New bit enters at LSB (
q[0]), old MSB (q[3]) is discarded - Declare
qasreg [3:0]
Topics
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Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
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