Synchronous Up/Down Counter with Load
Design a parameterized synchronous up/down counter in Verilog.
The counter supports four operations in priority order:
- Reset — synchronous active-high; forces
qto 0 andcarryto 0 - Load — parallel loads
dintoq - Count — increments (
up_down=1) or decrements (up_down=0)qby 1
Carry / Borrow
carry is asserted for exactly one cycle when the counter wraps around: • Overflow: counting up from 2^WIDTH - 1 → wraps to 0, carry = 1 • Underflow: counting down from 0 → wraps to 2^WIDTH - 1, carry = 1
The counter width is set by parameter WIDTH (default 4).
Priority Table
| reset | load | Action | |-------|------|------------------| | 1 | x | q = 0, carry = 0 | | 0 | 1 | q = d | | 0 | 0 | q = q ± 1 |
Constraints
- All state changes occur on the rising edge of
clk resethas highest priority (synchronous, active-high)loadhas second prioritycarryis registered — asserted for one cycle at wrap- Parameterized
WIDTHmust work for any positive integer - No latches allowed
Topics
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