Johnson Counter FF Count Verification
High-speed digital designs often require glitch-free state decoding or multi-phase clock generation. A Johnson counter, or twisted ring counter, achieves this by circulating an inverted stream of bits, providing 8 distinct states using only 4 flip-flops.
The module evaluates a 4-bit sequence. On every clock cycle, the current 4-bit value shifts left by one position. The new least significant bit is populated with the inverted value of the previous most significant bit.
The clock triggers on the positive edge. The reset is asynchronous and active-low. When reset is asserted, the output evaluates to 4'b0000. The output is registered. Priority is given to the asynchronous reset over the clock.
Cycle 1: rst_n=0 → out=4'b0000 (0) Cycle 2: rst_n=1 → out=4'b0001 (1) Cycle 3: rst_n=1 → out=4'b0011 (3) Cycle 4: rst_n=1 → out=4'b0111 (7) Cycle 5: rst_n=1 → out=4'b1111 (15) Cycle 6: rst_n=1 → out=4'b1110 (14) Cycle 7: rst_n=1 → out=4'b1100 (12) Cycle 8: rst_n=1 → out=4'b1000 (8) Cycle 9: rst_n=1 → out=4'b0000 (0)
{ "signal": [
{ "name": "clk", "wave": "p........." },
{ "name": "rst_n", "wave": "01........" },
{ "name": "out", "wave": "=.=.=.=.=.=.=.=.=.", "data": ["0","1","3","7","15","14","12","8","0"] }
], "head": { "text": "4-bit Johnson counter sequence (decimal values)" } }| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n| input | 1 | Asynchronous active-low reset; sets out to 4'b0000 | | out | output | 4 | Registered counter output |
Constraints
- Clock edge is
posedge. - Reset is asynchronous and active-low.
- Output resets to
4'b0000. - Shift direction is left;
out[0]receives the inverted value ofout[3]. - The design must infer exactly 4 flip-flops. Do not use a standard binary counter with combinational decoding.
Topics
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