Up Down Counter with Saturation

FIFO fill level trackers and digital audio volume controls rely on counters that hold their maximum or minimum values when limits are reached. A counter that wraps around from maximum capacity back to zero can cause catastrophic system states, such as a full FIFO reporting itself as empty.

This module tracks an 8-bit value based on directional control signals. It increments when the up signal is asserted and decrements when the down signal is asserted. To prevent overflow and underflow, the counter saturates. It halts at 255 when counting up and halts at 0 when counting down. If both control signals are asserted simultaneously, or if neither is asserted, the current value is held.

The circuit is driven by a positive-edge triggered clock. It features an asynchronous, active-low reset that clears the count to zero. All outputs are registered.

Cycle-by-cycle behaviour: Cycle 1: rst_n=0 → count=0 Cycle 2: rst_n=1, up=0, down=1 → count=0 (saturates at minimum) Cycle 3: rst_n=1, up=1, down=0 → count=1 Cycle 4: rst_n=1, up=1, down=1 → count=1 (hold due to simultaneous inputs) Cycle 5: rst_n=1, up=1, down=0 → count=2 Cycle 6: rst_n=1, up=0, down=1 → count=1 Cycle 7: rst_n=1, up=0, down=0 → count=1 (hold due to no inputs) Cycle 8: rst_n=1, up=1, down=0 → count=2

{ "signal": [
  { "name": "clk",   "wave": "p......." },
  { "name": "rst_n", "wave": "01......" },
  { "name": "up",    "wave": "00111001" },
  { "name": "down",  "wave": "01010100" },
  {},
  { "name": "count", "wave": "========", "data": ["0", "0", "1", "1", "2", "1", "1", "2"] }
], "head": { "text": "Counter operation showing saturation at zero and simultaneous input hold." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; clears count to 8'b00000000 | | up | input | 1 | Increment command | | down | input | 1 | Decrement command | | count | output | 8 | Current counter value; saturates at 8'hFF and 8'h00 |

Constraints

• The module must trigger on the positive edge of clk.
• The reset must be asynchronous and active-low.
• The counter must not wrap around under any circumstances; it must saturate at 255 for the maximum limit and 0 for the minimum limit.
• If up and down are both 1, the counter must hold its current value.
• If up and down are both 0, the counter must hold its current value.

Topics

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