Parameterized Modulo N Counter

Clock dividers, protocol timers, and PWM generators rarely operate on strict power-of-two boundaries. A modulo-N counter tracks elapsed cycles up to a specific limit before wrapping around, providing a precise timebase for downstream logic.

The module maintains a running count that increments every clock cycle when enabled. When the count reaches a configurable maximum value, it resets to zero on the following active clock edge. A tick pulse is generated combinatorially during the exact cycle the counter equals the maximum value, signaling to other modules that the terminal count has been reached.

• Clock edge: posedge clk
• Reset type: asynchronous active-low rst_n
• Output values on reset: count goes to 0; tick is evaluated combinatorially based on count and max_val
• Priority rules: Reset has highest priority. If en is low, the counter holds its current value without incrementing or wrapping.

Cycle 1: rst_n=0, en=0, max_val=2 → count=0, tick=0 Cycle 2: rst_n=1, en=1, max_val=2 → count=1, tick=0 Cycle 3: rst_n=1, en=1, max_val=2 → count=2, tick=1 Cycle 4: rst_n=1, en=0, max_val=2 → count=2, tick=1 (hold) Cycle 5: rst_n=1, en=1, max_val=2 → count=0, tick=0 (wrap) Cycle 6: rst_n=1, en=1, max_val=2 → count=1, tick=0 Cycle 7: rst_n=1, en=1, max_val=2 → count=2, tick=1

{ "signal": [
  { "name": "clk", "wave": "p......" },
  { "name": "rst_n", "wave": "01....." },
  { "name": "en", "wave": "0110111" },
  { "name": "max_val", "wave": "2......", "data": ["2"] },
  { "name": "count", "wave": "=======", "data": ["0", "1", "2", "2", "0", "1", "2"] },
  { "name": "tick", "wave": "0011001" }
], "head": { "text": "Modulo-2 counting with an enable stall at the terminal count." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; count goes to 0 when asserted | | en | input | 1 | Enable; counter increments or wraps on posedge clk when high | | max_val | input | WIDTH | The terminal value of the counter | | count | output | WIDTH | Current count value; resets to 0 | | tick | output | 1 | Combinational output; asserted high when count equals max_val |

Constraints

• The tick output must be purely combinational, not registered.
• The module must be parameterized with WIDTH defaulting to 8.
• The counter must reset to 0 synchronously when count equals max_val and en is high.
• The counter must hold its value when en is low, even if it is currently at max_val.
• Reset is asynchronous and active-low.

Topics

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