Free Running Up Counter

Counters are the foundation of all timers, clock dividers, and state machine timeouts in digital hardware. A free-running up counter simply increments its value on every clock cycle it is enabled, naturally wrapping back to zero upon reaching its maximum representable value.

This module maintains a 4-bit value that increments by one whenever the enable signal is asserted. When the counter reaches its maximum value of 15, the next increment rolls the value back to 0. If the enable signal is de-asserted, the counter holds its current value indefinitely.

• Clock edge: posedge clk
• Reset type: Asynchronous, active-low
• Output on reset: count becomes 4'b0000
• Priority: Reset has the highest priority. If rst_n is 0, the output evaluates to 0 regardless of the state of en.

Worked Trace: Cycle 1: rst_n=0, en=X → count=0 (reset) Cycle 2: rst_n=1, en=1 → count=1 (increment) Cycle 3: rst_n=1, en=1 → count=2 (increment) Cycle 4: rst_n=1, en=0 → count=2 (hold) Cycle 5: rst_n=1, en=1 → count=3 (increment)

{ "signal": [
  { "name": "clk",   "wave": "p...." },
  { "name": "rst_n", "wave": "01..." },
  { "name": "en",    "wave": "x1101" },
  {},
  { "name": "count", "wave": "=====", "data": ["0","1","2","2","3"] }
], "head": { "text": "Cycle-by-cycle counting and hold behavior." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; drives count to 0 when asserted | | en | input | 1 | Enable; counter increments on posedge clk while en=1 | | count | output | 4 | Current count value; resets to 4'b0000 |

Constraints

• The reset must be asynchronous and active-low.
• The counter must naturally wrap from 4'b1111 to 4'b0000 without requiring an explicit reset.
• count must be a registered output.
• The module must handle enable de-assertion by holding the exact value from the previous clock cycle.

Topics

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