Bidirectional Arithmetic Shift Register
Digital signal processing datapaths frequently rely on arithmetic shifts to multiply or divide signed integers by powers of two without consuming expensive multiplier resources. The bidirectional arithmetic shift register holds an 8-bit value that can be loaded in parallel or shifted serially. When shifting left, the serial input fills the least significant bit. When shifting right, the behavior depends on the arithmetic control flag. A logical right shift fills the most significant bit with the serial input. An arithmetic right shift ignores the serial input and replicates the current most significant bit (the sign bit) to preserve the sign of the two's complement value.
The module operates on the positive edge of clk and features an asynchronous active-low reset rst_n. The parallel load signal has priority over the shift en signal. When load is asserted, the register captures d_in. When load is de-asserted and en is asserted, the register shifts its contents based on the dir (direction) and arith (arithmetic) flags. If neither load nor en are asserted, the register holds its current value. Left shifts always shift in s_in to the LSB, regardless of the arith flag.
- Cycle 1:
rst_n=0→q_out=8'h00(asynchronous reset) - Cycle 2:
rst_n=1,load=1,d_in=8'hA5→q_out=8'hA5at clock edge - Cycle 3:
load=0,en=1,dir=0,arith=1→q_out=8'hD2at clock edge - Cycle 4:
en=1,dir=0,arith=1→q_out=8'hE9at clock edge - Cycle 5:
en=1,dir=1,s_in=1→q_out=8'hD3at clock edge - Cycle 6:
en=1,dir=0,arith=0,s_in=0→q_out=8'h69at clock edge - Cycle 7:
en=0→q_out=8'h69(hold) at clock edge
{
"signal": [
{ "name": "clk", "wave": "P......." },
{ "name": "rst_n", "wave": "01......" },
{ "name": "load", "wave": "x10....." },
{ "name": "en", "wave": "x011110." },
{ "name": "dir", "wave": "xx0010.." },
{ "name": "arith", "wave": "xx11x0.." },
{ "name": "s_in", "wave": "xxxx10.." },
{ "name": "d_in", "wave": "x=......", "data": ["8'hA5"] },
{},
{ "name": "q_out", "wave": "2.22222.", "data": ["8'h00", "8'hA5", "8'hD2", "8'hE9", "8'hD3", "8'h69"] }
]
}| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; drives q_out to 8'b00000000 | | en | input | 1 | Shift enable; shifts q_out on posedge clk when 1 and load is 0 | | load | input | 1 | Synchronous parallel load; overrides en | | dir | input | 1 | Shift direction; 1 for left shift, 0 for right shift | | arith | input | 1 | Arithmetic shift flag; when 1 during a right shift, replicates the MSB | | s_in | input | 1 | Serial input; shifted into LSB on left shift, or MSB on logical right shift | | d_in | input | 8 | Parallel data input loaded when load is 1 | | q_out | output | 8 | Registered shift register output |
Constraints
- Clock edge and reset polarity:
posedge clk, asynchronous active-lowrst_n. - Output values on reset:
q_outmust be exactly8'b00000000. - Priority when multiple inputs are simultaneously asserted:
rst_n>load>en. - Left shifts always shift in
s_into the LSB, regardless of thearithflag. - Right shifts with
arith=1ignores_inand replicate the current MSB (q_out[7]).
Topics
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