Parallel In Serial Out with Load Control
UART transmitters and SPI controllers depend on parallel-in serial-out (PISO) shift registers to serialize byte-wide data for transmission over a single wire. This module acts as the serialization engine, multiplexing between capturing a full byte from the system and shifting it out bit-by-bit to the peripheral.
The module maintains an internal 8-bit register. When the load signal is asserted, it captures the parallel input byte. When the shift enable signal is asserted, it shifts the data left by one bit, outputting the most significant bit (MSB) and shifting in a zero at the least significant bit (LSB). The load operation takes strict priority over the shift operation if both are asserted simultaneously. The serial output continuously reflects the MSB of the internal register.
Timing and Reset Rules: • Clock edge: posedge clk • Reset type: Asynchronous • Reset polarity: Active-low (rst_n) • Reset behavior: The internal register clears to 8'b00000000, causing s_out to become 0 • Priority: load takes priority over shift_en
Worked Trace: Cycle 1: rst_n=0 → reg=8'h00, s_out=0 Cycle 2: rst_n=1, load=1, d_in=8'hA5, shift_en=0 → reg=8'hA5, s_out=1 Cycle 3: load=0, shift_en=1 → reg=8'h4A, s_out=0 (shifted left) Cycle 4: shift_en=0 → reg=8'h4A, s_out=0 (hold) Cycle 5: load=1, shift_en=1, d_in=8'hC3 → reg=8'hC3, s_out=1 (load overrides shift)
{ "signal": [
{ "name": "clk", "wave": "p....." },
{ "name": "rst_n", "wave": "01...." },
{ "name": "load", "wave": "01001." },
{ "name": "shift_en", "wave": "00101." },
{ "name": "d_in", "wave": "x==xx=", "data": ["8'hA5", "8'hA5", "8'hC3"] },
{},
{ "name": "reg", "wave": "=.=.=.", "data": ["00", "A5", "4A", "4A", "C3"] },
{ "name": "s_out", "wave": "010.1." }
], "head": { "text": "Reset, load, shift, hold, and load overriding shift." } }| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; clears register to 8'b0 | | load | input | 1 | Active-high load enable; captures d_in into the register | | shift_en | input | 1 | Active-high shift enable; shifts register left by one bit | | d_in | input | 8 | Parallel data input byte | | s_out | output | 1 | Serial data output; continuously reflects the MSB of the register |
Constraints
- The module must implement an asynchronous active-low reset.
- The
loadsignal must override theshift_ensignal if both are asserted on the same clock edge. - The shift operation must be a logical left shift, shifting in a
0at the LSB. - The
s_outsignal must continuously output the MSB (bit 7) of the internal register, including immediately upon reset.
Topics
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