Parameterized Serial In Parallel Out

EasyVerilog / SystemVerilogBuild

Serial protocols like SPI and UART transmit data one bit at a time, but internal data paths process full multi-bit words. A Serial-In Parallel-Out (SIPO) shift register bridges this gap by accumulating incoming bits over multiple clock cycles and exposing them as a parallel bus. Hardcoding the width of this buffer restricts reuse across different protocol standards.

This module accumulates a continuous stream of serial bits into a parallel output register. The width of the parallel output is defined by a parameter WIDTH. When the enable signal is asserted, the register shifts its current contents to the left. The existing Most Significant Bit (MSB) is discarded, and the new serial input bit is loaded into the Least Significant Bit (LSB) position. The parallel output continuously reflects the current state of the shift register.

Timing and Reset Rules

Clock edge: posedge clk
Reset type: asynchronous
Reset polarity: active-low rst_n
Output values on reset: all bits of data_out go to 0
Priority rules: Asynchronous reset takes precedence over the clock and enable signals. When en is 0, the register holds its current value regardless of serial_in.

Worked Trace (WIDTH=4)

Cycle 1: rst_n=0 → data_out=4'b0000
Cycle 2: rst_n=1, en=1, serial_in=1 → data_out=4'b0001 (1)
Cycle 3: rst_n=1, en=1, serial_in=0 → data_out=4'b0010 (2)
Cycle 4: rst_n=1, en=0, serial_in=1 → data_out=4'b0010 (hold)
Cycle 5: rst_n=1, en=1, serial_in=1 → data_out=4'b0101 (5)
Cycle 6: rst_n=1, en=1, serial_in=1 → data_out=4'b1011 (11)

Diagrams

{ "signal": [
  { "name": "clk",       "wave": "p......" },
  { "name": "rst_n",     "wave": "01....." },
  { "name": "en",        "wave": "01.011." },
  { "name": "serial_in", "wave": "x10111x" },
  {},
  { "name": "data_out",  "wave": "0.=====", "data": ["1", "2", "2", "5", "11"] }
], "head": { "text": "4-bit SIPO Shift Register Operation" } }

Port Table

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; clears data_out to 0 | | en | input | 1 | Shift enable; shifts data left and loads serial_in to LSB when 1 | | serial_in | input | 1 | Serial data input | | data_out | output | WIDTH | Parallel data output |

Constraints

The module must declare a parameter WIDTH with a default value of 8.
Clock must be posedge clk.
Reset must be asynchronous and active-low.
When en is high, the register shifts left: data_out[0] receives serial_in, and data_out[WIDTH-1] is discarded.
When en is low, data_out must hold its current value.

Topics

sequentialshift-registerparameter

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