Priority Control: Reset Overrides Enable Overrides Load
Control logic in hardware often receives multiple conflicting commands on the same clock cycle. A register file or program counter might receive a command to increment and a command to load a branch address simultaneously. Without a strict priority hierarchy, the circuit will exhibit unpredictable behavior or synthesis mismatches.
This module is an 8-bit counter that enforces a strict priority hierarchy among its control signals. When the enable signal is asserted, the counter increments by 1. When the load signal is asserted, the counter loads the value from the data input. If neither is asserted, the counter holds its current value. If both enable and load are asserted simultaneously, the enable signal takes priority and the counter increments, ignoring the load command.
Timing and Reset Rules: • Clock edge: posedge • Reset type: Asynchronous • Reset polarity: Active-low • Output values on reset: count goes to 8'b00000000 • Priority hierarchy: Asynchronous rst_n overrides synchronous en; synchronous en overrides synchronous load.
Worked Trace: • Cycle 1: rst_n=0 → count=0 (Reset overrides all) • Cycle 2: rst_n=1, en=0, load=1, data_in=10 → count=10 (Load operation) • Cycle 3: rst_n=1, en=1, load=1, data_in=20 → count=11 (Enable overrides load) • Cycle 4: rst_n=1, en=0, load=0, data_in=20 → count=11 (Hold value) • Cycle 5: rst_n=1, en=0, load=1, data_in=55 → count=55 (Load operation) • Cycle 6: rst_n=1, en=1, load=0, data_in=55 → count=56 (Increment operation) • Cycle 7: rst_n=0, en=1, load=1, data_in=99 → count=0 (Reset overrides all) • Cycle 8: rst_n=1, en=0, load=0, data_in=99 → count=0 (Hold value)
{ "signal": [
{ "name": "clk", "wave": "p......." },
{ "name": "rst_n", "wave": "01111101" },
{ "name": "en", "wave": "00100110" },
{ "name": "load", "wave": "01101010" },
{ "name": "data_in", "wave": "x==.=.=.", "data": ["10", "20", "55", "99"] },
{},
{ "name": "count", "wave": "===.===.", "data": ["0", "10", "11", "55", "56", "0"] }
], "head": { "text": "Cycle-by-cycle trace showing priority hierarchy." } }| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; drives count to 0 | | en | input | 1 | Enable; increments count by 1 on posedge clk | | load | input | 1 | Load; sets count to data_in on posedge clk when en is 0 | | data_in | input | 8 | Data to be loaded into the counter | | count | output | 8 | Current counter value |
Constraints
- Clock edge must be positive.
- Reset must be asynchronous and active-low.
- Output must be exactly 8 bits wide.
- Enable must override load when both are asserted simultaneously.
- Counter must wrap back to 0 automatically when incrementing past 255.
Topics
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