Multi Byte Enable Register

CPU register files and memory-mapped peripherals frequently require partial word updates. A 32-bit data bus often carries byte-enable signals to allow updating a single byte or half-word without reading, masking, and rewriting the entire 32-bit word.

This module maintains a 32-bit registered output. On every clock cycle, it evaluates a 4-bit byte-enable signal. Each bit of the byte-enable signal corresponds to one byte of the 32-bit input data. If a byte-enable bit is asserted, the corresponding byte in the register is updated with the new input byte. If the bit is deasserted, the corresponding byte retains its previous value.

The circuit operates on the positive edge of clk. It uses a synchronous, active-low reset rst_n. When rst_n is 0, the entire 32-bit register is cleared to 0, regardless of the byte_en state. Priority is always given to the reset signal.

Cycle 1: rst_n=0, byte_en=4'b1111, data_in=32'hFFFFFFFF → data_out=32'h00000000 (Reset) Cycle 2: rst_n=1, byte_en=4'b0001, data_in=32'hAABBCCDD → data_out=32'h000000DD (Byte 0 updated) Cycle 3: rst_n=1, byte_en=4'b1000, data_in=32'h11223344 → data_out=32'h110000DD (Byte 3 updated) Cycle 4: rst_n=1, byte_en=4'b0110, data_in=32'h99887766 → data_out=32'h118877DD (Bytes 1 and 2 updated) Cycle 5: rst_n=1, byte_en=4'b0000, data_in=32'hFFFFFFFF → data_out=32'h118877DD (Hold)

{ "signal": [
  { "name": "clk",      "wave": "p....." },
  { "name": "rst_n",    "wave": "01...." },
  { "name": "byte_en",  "wave": "======", "data": ["4'hF", "4'h1", "4'h8", "4'h6", "4'h0", "4'h0"] },
  { "name": "data_in",  "wave": "======", "data": ["32'hFFFFFFFF", "32'hAABBCCDD", "32'h11223344", "32'h99887766", "32'hFFFFFFFF", "32'hFFFFFFFF"] },
  {},
  { "name": "data_out", "wave": "======", "data": ["32'h00000000", "32'h000000DD", "32'h110000DD", "32'h118877DD", "32'h118877DD", "32'h118877DD"] }
], "head": { "text": "Cycle-by-cycle register updates based on byte enables" } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Synchronous active-low reset; clears data_out to 0 | | byte_en | input | 4 | Byte enable mask; bit 0 controls bytes 7:0, bit 1 controls 15:8, etc. | | data_in | input | 32 | 32-bit input data bus | | data_out | output | 32 | 32-bit registered output |

Constraints

• The module must trigger on the positive edge of clk.
• The reset rst_n must be synchronous and active-low.
• On reset, the entire 32-bit data_out register must be cleared to 0.
• Synchronous reset has strict priority over any byte enable signals.
• data_out must be a registered output, updating only on the clock edge.
• byte_en[0] controls data_out[7:0]; byte_en[1] controls data_out[15:8]; byte_en[2] controls data_out[23:16]; byte_en[3] controls data_out[31:24].

Topics

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