Basic Clock Enable Register
Data pipelines rely heavily on clock enables to stall stages when downstream buffers are full or data is invalid. Gating the clock directly introduces timing skew and glitches, making synchronous clock enables the standard practice for controlling data flow in modern digital design.
The solution module captures the input data on the rising edge of the clock only when the enable signal is asserted. When the enable is de-asserted, the module retains its current value, ignoring any changes on the data input.
The module is driven by a positive-edge triggered clock clk and an asynchronous active-low reset rst_n. On reset, the output q must be cleared to 0. The reset signal has the highest priority; if rst_n is asserted, the output must clear immediately regardless of the state of the clock or the enable signal.
Cycle 1: rst_n=0 → q=0 Cycle 2: rst_n=1, en=1, d=170 → q=170 Cycle 3: rst_n=1, en=0, d=187 → q=170 (hold) Cycle 4: rst_n=1, en=1, d=204 → q=204
{ "signal": [
{ "name": "clk", "wave": "p...." },
{ "name": "rst_n", "wave": "01..." },
{ "name": "en", "wave": "01010" },
{ "name": "d", "wave": "x====", "data": ["170", "187", "204", "255"] },
{ "name": "q", "wave": "=.=.=", "data": ["0", "170", "204"] }
], "head": { "text": "Register updates only when enable is high." } }| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; output goes to 0 when asserted | | en | input | 1 | Active-high enable; register captures d on posedge clk when en=1 | | d | input | 8 | Data input | | q | output | 8 | Data output; resets to 8'b00000000 |
Constraints
- The module must trigger on the positive edge of
clk. - The reset
rst_nmust be asynchronous and active-low. - Output
qmust initialize to8'b00000000on reset. - The enable logic must be implemented in the data path rather than gating the clock signal.
- Reset has priority over the enable signal.
Topics
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