Dual Reset: Async Hard Clear and Sync Soft Clear

Complex state machines and data pipelines often require a system-wide asynchronous reset for power-on initialization, alongside a local synchronous clear to abort or restart operations on the fly. Combining these safely on a single register requires careful attention to priority and clock domains to avoid race conditions.

The dual_reset_reg module maintains an 8-bit register that captures the input data on every active clock edge. It features two distinct reset mechanisms. The asynchronous hard reset immediately forces the register to zero regardless of the clock. The synchronous soft clear forces the register to zero on the next active clock edge. When both reset signals are asserted simultaneously, the asynchronous reset takes absolute priority.

Timing and Reset Rules

• Clock edge: posedge clk
• Asynchronous reset: rst_n is active-low. When asserted, q immediately becomes 8'h00.
• Synchronous clear: clr is active-high. When asserted, q becomes 8'h00 on the next posedge clk.
• Priority rules: rst_n has absolute priority over both clr and d. The clr signal has priority over d.
• Registered output: q must be strictly registered and only change on posedge clk or when rst_n is asserted.

Worked Trace

Cycle 1: rst_n=0, clr=X, d=X → q=0 (Asynchronous reset forces output to 0 immediately) Cycle 2: rst_n=1, clr=0, d=5 → q=5 (Normal data load on clock edge) Cycle 3: rst_n=1, clr=1, d=9 → q=0 (Synchronous clear forces output to 0 on clock edge) Cycle 4: rst_n=1, clr=0, d=7 → q=7 (Normal data load on clock edge) Cycle 5: rst_n=0, clr=1, d=3 → q=0 (Asynchronous reset overrides synchronous clear)

Waveform

{ "signal": [
  { "name": "clk",   "wave": "p........" },
  { "name": "rst_n", "wave": "01......0" },
  { "name": "clr",   "wave": "x0.10...1" },
  { "name": "d",     "wave": "x=...=.=.", "data": ["5", "9", "7", "3"] },
  {},
  { "name": "q",     "wave": "=.=..=.=.", "data": ["0", "5", "0", "7", "0"] }
], "head": { "text": "Register behaviour with async reset and sync clear." } }

Port Table

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n| input | 1 | Asynchronous active-low reset; forces q to 0 immediately | | clr | input | 1 | Synchronous active-high clear; forces q to 0 on the next clock edge | | d | input | 8 | Data input | | q | output | 8 | Registered data output; resets to 8'h00 |

Constraints

• The rst_n signal must be evaluated asynchronously.
• The clr signal must be evaluated synchronously.
• The rst_n signal must take priority over clr.
• The clr signal must take priority over d.
• The output q must be 8 bits wide and default to 0 on reset.

Topics

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