Parameterized Interface with Modports

Modern System-on-Chip (SoC) architectures rely heavily on standardized protocols like AXI Stream to move data between IP blocks. Because data widths vary across the system—for example, a 32-bit CPU communicating with an 8-bit UART—engineers use SystemVerilog interfaces with parameters and modports to define reusable, type-safe bus connections. Passing an interface through a module port ensures that all protocol signals stay bundled together, preventing mismatches and reducing boilerplate code.

The system consists of three modules and one interface. The axis_if interface encapsulates a simplified AXI Stream protocol. The producer module receives data from the external system and initiates a transfer across the interface. The consumer module listens on the interface, accepts the transfer, and outputs the received data to the external system. The solution module is the top-level wrapper that instantiates the interface and connects the producer and consumer together.

Timing and reset rules: • Clock edge: clk is positive-edge triggered. • Reset type: rst_n is asynchronous and active-low. • Reset behavior: On reset, producer must drive tvalid to 0. consumer must drive done to 0, data_out to 0, and continuously drive tready to 1. • Normal operation (producer): When start is 1, it captures data_in into an internal register. On the next clock cycle, it asserts tvalid to 1 and places the captured data on tdata. It holds tvalid high until tready is 1. • Normal operation (consumer): It continuously drives tready to 1. When it detects tvalid is 1, it captures tdata into data_out and asserts done to 1 on the following clock cycle. The done signal is a one-cycle pulse. • Priority: If start is asserted during reset, the reset takes priority and no transfer initiates.

Cycle-by-cycle worked trace: • Cycle 1: rst_n=0 → producer tvalid=0. consumer tready=1, done=0, data_out=0. • Cycle 2: rst_n=1 → System idle. start=1, data_in=0xAA. • Cycle 3: start=0 → producer asserts tvalid=1, tdata=0xAA. consumer sees tvalid=1 and tready=1. • Cycle 4: producer sees tready=1, drops tvalid=0. consumer asserts done=1, updates data_out=0xAA. • Cycle 5: consumer sees tvalid=0, drops done=0. data_out holds 0xAA.

{ "signal": [
  { "name": "clk", "wave": "p......" },
  { "name": "rst_n", "wave": "01....." },
  { "name": "start", "wave": "0.10..." },
  { "name": "data_in", "wave": "x.==x..", "data": ["0xAA", "0xAA"] },
  {},
  { "name": "intf.tvalid", "wave": "0..10.." },
  { "name": "intf.tready", "wave": "01....." },
  { "name": "intf.tdata", "wave": "x..=x..", "data": ["0xAA"] },
  {},
  { "name": "done", "wave": "0...10." },
  { "name": "data_out", "wave": "==..=..", "data": ["0x00", "0x00", "0xAA"] }
], "head": { "text": "Cycle-by-cycle interface transfer" } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset | | start | input | 1 | Initiates a transfer from the producer | | data_in | input | WIDTH | Data to be transferred | | done | output | 1 | One-cycle pulse indicating consumer received data | | data_out | output | WIDTH | Data received by the consumer; resets to 0 |

Constraints

• The axis_if interface must be parameterized by DATA_WIDTH (default 32).
• The axis_if interface must take clk and rst_n as interface ports.
• The axis_if interface must declare exactly three logic signals: tvalid, tready, and tdata.
• The axis_if interface must define a master modport (outputs: tvalid, tdata; inputs: tready, clk, rst_n).
• The axis_if interface must define a slave modport (outputs: tready; inputs: tvalid, tdata, clk, rst_n).
• The producer module must NOT have clk and rst_n in its module port list. It must extract them from the m_axis modport.
• The consumer module must NOT have clk and rst_n in its module port list. It must extract them from the s_axis modport.
• The solution module must instantiate axis_if, producer, and consumer, passing the WIDTH parameter to all three.

Topics

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