Elaboration Time Generate Failure
A configurable delay element buffers an input signal through a flip-flop for timing synchronization in one configuration, or passes it combinationally in another. Parameterized generate blocks are the standard RTL technique for selecting between two structural implementations at compile time without duplicating module code.
The solution module is parameterized with bypass. When bypass is 0 the module registers d through a flip-flop and drives q one cycle later. When bypass is 1 the module drives q directly from d combinationally.
The compiler halts with an elaboration error: "Identifier is not a constant." The test suite fails to build. Inspect the code and correct the fault. The testbench instantiates the module with bypass = 0.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock; used only when bypass=0 | | d | input | 1 | Data input | | q | output | 1 | Data output; registered when bypass=0, combinational when bypass=1 |
Constraints
- The configuration must be a compile-time parameter, not a runtime input port.
- When
bypass = 0, the flip-flop is positive-edge triggered and has no reset. - When
bypass = 1, outputqequals inputdcombinationally with no clock dependency. - Do not change the internal logic; only change how
bypassis declared.
Topics
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