Vector Port Endianness
Hardware subsystems frequently integrate IP blocks from different vendors, which can lead to mismatched bit-numbering conventions. Some architectures use descending indices (e.g., [7:0]) where index 7 is the most significant bit, while others use ascending indices (e.g., [0:7]) where index 0 is the most significant bit. Connecting these modules incorrectly causes silent bit-reversal bugs that are notoriously difficult to debug in simulation.
The solution module must accept an 8-bit input vector using descending bit indices and drive an 8-bit output vector using ascending bit indices. Connect the input directly to the output using a continuous assignment. Because Verilog matches bits positionally from left to right during assignment, the leftmost bit of the input will automatically map to the leftmost bit of the output, regardless of the index numbers.
To verify that your output vector is declared with the correct index order, you must also expose bit 3 of your output vector on a separate 1-bit probe port.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | in_vec | input | 8 | Input vector, declared with descending indices [7:0] | | out_vec | output | 8 | Output vector, declared with ascending indices [0:7] | | out_vec_3 | output | 1 | Probe port; must be assigned the exact value of out_vec[3] |
Constraints
- The
in_vecport must be declared with descending indices[7:0]. - The
out_vecport must be declared with ascending indices[0:7]. - The
out_vec_3port must exactly reflect the value ofout_vec[3]. - All outputs must be purely combinational.
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