Port Width Mismatch
An 8-bit arithmetic logic unit computes the bitwise AND of two 8-bit buses to mask control signals. The masking unit sits between a register file read port and a downstream execution stage. Full 8-bit precision is required; losing the upper nibble corrupts every operation that touches the high byte.
The solution module must accept two 8-bit inputs A and B and drive an 8-bit output Y equal to their bitwise AND. The circuit is purely combinational. There is no clock or reset.
Simulation shows Y = 15 for inputs A = 255 and B = 255. The upper four bits of the output evaluate to zero instead of retaining their expected high state. Inspect the code and correct the fault.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | A | input | 8 | First operand | | B | input | 8 | Second operand | | Y | output | 8 | Bitwise AND result; must reflect all 8 bits |
Constraints
- Do not change the top-level module interface.
- The output must be strictly combinational; no clock or flip-flops.
- Ensure all internal wire declarations match the widths of the ports they connect to.
Topics
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Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
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