Wire versus Reg in Continuous Assignment

A 2-to-1 multiplexer routes one of two input data streams to a single output based on a control signal. Multiplexers of this form appear at the input of every ALU operand path and at the output of every write-back stage in a processor pipeline. The implementation uses a continuous assignment driven from a ternary expression.

The solution module accepts inputs A, B and Sel and drives output Out. When Sel is 0 the output follows A. When Sel is 1 the output follows B.

The compiler throws a syntax error during elaboration. The log reports an illegal left-hand side in the continuous assignment for Out. The simulation cannot start. Inspect the code and correct the fault.

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | Sel | input | 1 | Select signal; 0 selects A, 1 selects B | | A | input | 1 | Data input 0 | | B | input | 1 | Data input 1 | | Out | output | 1 | Selected output; purely combinational |

Constraints

• Do not change the boolean logic or the assign keyword.
• Do not convert the logic into an always block.
• The output must be strictly combinational; no latches or flip-flops.

Topics

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