Inout Port Mechanics
External memory interfaces and shared system buses rely on bidirectional pins to save physical package constraints. A single physical trace acts as both a transmitter and a receiver depending on the bus phase.
The module controls an 8-bit bidirectional data line. When the module is transmitting, it drives the external data line with its internal transmit data. When the module is receiving, it must release the bus by driving a high impedance state, allowing other external devices to drive the line safely without electrical contention. The module simultaneously monitors the external data line and routes its current state to an internal receive data port.
Timing and Reset Rules: • Purely combinational logic; no clock or reset signals are used. • Output values reflect inputs immediately. • High impedance must be driven to the bidirectional bus when not actively transmitting.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | tx_en | input | 1 | Transmit enable; when 1, the module drives bus_io | | tx_data | input | 8 | Internal data to be transmitted | | rx_data | output | 8 | Internal data received from the bus | | bus_io | inout | 8 | External bidirectional bus |
Constraints
bus_iomust be driven to8'bzzzzzzzzwhentx_enis0.rx_datamust continuously reflect the resolved state ofbus_io.- Purely combinational logic; no latches or registers.
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