Parameterized Module Width
IP reuse is a fundamental principle of modern hardware design. Hardcoding bus widths forces engineers to maintain multiple versions of identical logic for different subsystems. Parameterised modules allow a single RTL description to scale seamlessly across 8-bit, 32-bit, or 64-bit datapaths without code duplication.
This module computes the arithmetic sum of two unsigned input vectors. The bit width of the inputs and the resulting sum is defined by a parameter named WIDTH. The module must output the sum and a single-bit carry-out flag that asserts when the addition overflows the parameterised width.
| Parameter | Type | Default | Description | |-----------|------|---------|-------------| | WIDTH | integer | 8 | Bit width of the operands and sum |
| Signal | Direction | Width | Description | |--------|-----------|---------|-------------| | a | input | WIDTH | First unsigned operand | | b | input | WIDTH | Second unsigned operand | | sum | output | WIDTH | Arithmetic sum of a and b | | cout | output | 1 | Carry out from the most significant bit |
Constraints
- The module must declare a parameter
WIDTHwith a default value of 8 - The addition must be purely combinational
- The
coutsignal must accurately reflect the carry-out of the most significant bit for the instantiatedWIDTH - Input vectors
aandbmust be treated as unsigned integers
Topics
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Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
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