Parameterized Vector Slicing
Packet parsers and network routers frequently extract specific fields from wide data buses using dynamic offsets. A common operation in these systems is sliding a fixed-width window across a larger data word to capture a specific byte based on a calculated index.
The module receives a 32-bit data word and a dynamically changing 5-bit offset. It evaluates the inputs combinationally and extracts an 8-bit slice starting exactly at the specified bit offset.
This is a purely combinational circuit. There are no clock or reset signals. The output updates immediately when any input changes.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | data_in | input | 32 | The full data word to be sliced | | offset | input | 5 | The starting bit index for the extraction | | data_out | output | 8 | The extracted 8-bit slice starting at offset |
Constraints
- The circuit must be purely combinational.
- The
offsetinput is guaranteed to be in the range 0 to 24; you do not need to handle out-of-bounds indices. - You must dynamically slice the input vector based on the variable
offset.
Topics
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Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
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