Byte Swapping via Concatenation
Network interfaces and cross-platform communication bridges frequently need to translate data between different endianness formats. Network byte order is typically big-endian, while many modern processors operate natively in little-endian.
The module receives a 32-bit data word and reverses the order of its four bytes. This operation swaps the most significant byte with the least significant byte, and the second-most significant byte with the second-least significant byte. The bits within each byte must remain in their original order.
This is a purely combinational logic circuit. The output updates immediately when the input changes.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | in_word | input | 32 | The 32-bit input data word to be swapped. | | out_word | output | 32 | The 32-bit output data word with reversed byte order. |
Constraints
- The design must be strictly combinational; do not use clocks, registers, or latches.
- The implementation must use the Verilog concatenation operator
{}. - The bit order within each individual 8-bit byte must remain unchanged.
Topics
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Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
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