1-bit ALU with Function Select (AND / OR / XOR / ADD)
The Arithmetic Logic Unit is the computational heart of every processor. At its core, an ALU is a multiplexed collection of functional units — each operation (AND, OR, XOR, ADD) is computed in parallel, and the function-select bits choose which result to pass to the output. This problem asks you to build the simplest possible version: a 1-bit ALU that supports four operations selected by a 2-bit function code.
Given two 1-bit data inputs A and B and a 2-bit function select F = {F1, F0}, the output Y is:
F1=0, F0=0 → Y = A AND B F1=0, F0=1 → Y = A OR B F1=1, F0=0 → Y = A XOR B F1=1, F0=1 → Y = A XOR B (sum bit of 1-bit addition; Cout is not an output of this problem)
Worked examples: with A=1, B=1 and F=00 (AND), Y=1. With A=1, B=0 and F=01 (OR), Y=1. With A=1, B=1 and F=10 (XOR), Y=0. With A=0, B=1 and F=11 (ADD sum), Y=1.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | A | input | 1 | First operand | | B | input | 1 | Second operand | | F1 | input | 1 | Function select MSB | | F0 | input | 1 | Function select LSB | | Y | output | 1 | Result of the selected operation |
Constraints
- The circuit is purely combinational. No clock or state.
- No carry-out output is required. The ADD operation only produces the sum bit (A XOR B).
- The optimal solution uses 5 components: 1 AND gate, 1 OR gate, 1 XOR gate, and 2 MUX 2:1 components.
- Operations F=10 and F=11 both produce A XOR B, so a single XOR gate serves both. The MUX tree routes the correct result based on F1 and F0.
Topics
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